Synopsys DesignWare ARC AXC003, Руководство пользователя, Страница: 111 / 145

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Clock-Generation Registers DesignWare ARC AXC003 CPU Card User Guide
Version 6323-018 Synopsys, Inc.
May 2017
LOCK PLL lock indication
0
= PLL is unlocked
1
= PLL is locked
ERROR PLL error indication. Asserted high to to indicate that PLL was programmed
with an illegal value. PLL can be re-programmed after the ERROR status
bit is reset to
0
ARC PLL
Reference input clock for ARC PLL is 33Mhz
Minimum input clock frequency is 10MHz
VCO range for ARC PLL is 600 - 1440MHz
9.1.2.1 ARC_PLL_IDIV Register
31 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reserved NOUPDATE BYPASS EDGE HIGHTIME LOWTIME
Address offset: 0x0080
Reset Value: 0x0000_2041 (0x0000_3001 after pre-boot)
Access: RW
Register to control setting of the ARC PLL input divider
LOWTIME[5:0] sets the amount of time in input cycles that the divided input clock remains
low
HIGHTIME[5:0] sets the amount of time in input cycles that the divided input clock remains
high
IDIV = L HIGHTIME
EDGE chooses the edge that the High Time counter transitions on (
0
=rising,
1
=falling)
BYPASS bypass the input divider
NOUPDATE prevent update of the PLL with new settings. Debug only; can be used for
register RW test
To obtain a 50% duty-cycle the divider shall be programmed as follows:
- even divider ratio => LOWTIME = HIGHTIME
EDGE =
0