Supermicro X10SRG-F, Руководство пользователя

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2-24
X10SRG-F Motherboard User’s Manual
A. Wake On LAN
B. System Management Bus
A
B
Legacy Wake-On-LAN Header
(JSTBY1)
The onboard LANs (LAN1 and LAN2)
do not need WOL header to sup-
port its Wake-On-LAN function. We
preserved the legacy WOL header
to provide convenience for some
embedded customers who need in-
ternal power source from the board.
See the table on the right for pin
definitions.
Wake-On-LAN
(JSTBY1)
Pin Definitions
Pin# Definition
1 +5V Standby
2 Ground
3 Wake-up
System Management Bus
(JIPMB1
)
A System Management Bus header
for the IPMI slot is located at JIPMB1.
Connect the appropriate cable here
to use the IPMB I2C connection on
your system.
System Management
Bus (JIPMB1)
Pin# Definition
1 Data
2 Ground
3 Clock
4 No Connection
X10SRG-F
REV:1.01
DESIGNED IN USA
BIOS
LICENSE
MAC CODE
IPMI CODE
BAR CODE
4
1
JVRM2 JVRM1
Intel C610
BMC
i350
JUIDB1
FA
ND
FA
N4
FA
N3
FA
N2
FA
N1
FA
NC
FA
NA
FA
NB
JTPM1
JL
1
JOH1
LE2
LE1
LEDM1
S-SA
TA
3
S-SA
TA
2
S-SA
TA
1
S-SA
TA
0
I-SA
TA
4
I-SA
TA
3
I-SA
TA
5
I-SA
TA
2I
-SA
TA
1
I-SA
TA
0
JSTBY1
JPCIE
2
JPCIE
3
JSD
1
JSD
2
JPW3
JPW2
JPW
1
I-SGPIO2
I-SGPIO1
S-SGPI
O
JIPMB1
JP3
JD
1
JPI2C1
JPL1
JPB1
JI2C2
JWD1 JPME2
JI2C1
JBRSET1
JBR
1
JPL_LAN1 JPL_LAN0
JPL_LOM_DEV_OF
F
JPG1
JVR1
JPF
1
JPF
2
BT1
SP1
JP4
JITP1
J2
3
JPCIE
3
JF
1
SXB1
B
USB 8/9(3.0)
USB 6/7
USB 4/5
USB 2/
3
S
ATA
DOM+POWE
R
S
ATA
DOM+POWE
R
UID-SW
COM2
IPMI_LAN
VGA
CPU SLOT3 PCI-E 3.0 X8(IN X16)
SXB2
B
SXB2A
SXB1A
JBT1
PWR
JF1
ON
RST
2
NIC
1
NIC
FF
OH
LED LED
PWR HDD X NMI
DIMMB2 DIMMA1 DIMMB1 DIMMA2
LAN1 LAN2
DIMMD
2
DIMMC
1
DIMMD
1
DIMMC
2
COM1
USB 0/1(3.0)
CPU
LGA2011-3
1
1