Smart Machine Smart Decision
SIM5800_Hardware Design_V1.01
46
2018-10-08
Pin
Signal
Length(mm)
Error in length
（
P-N
）
52
MIPI_DSI_CLKN
12.04
0.14
53
MIPI_DSI_CLKP
12.18
54
MIPI_DSI_L0N
12.98
0.42
55
MIPI_DSI_L0P
13.40
56
MIPI_DSI_L1N
12.48
-0.55
57
MIPI_DSI_L1P
11.93
58
MIPI_DSI_L2N
13.50
-0.11
59
MIPI_DSI_L2P
13.39
63
MIPI_CSI0_CLKN
18.78
0.33
64
MIPI_CSI0_CLKP
19.11
65
MIPI_CSI0_L0N
18.90
0.48
66
MIPI_CSI0_L0P
19.38
67
MIPI_CSI0_L1N
19.63
0.56
68
MIPI_CSI0_L1P
20.19
70
MIPI_CSI1_CLKN
22.89
-0.52
71
MIPI_CSI1_CLKP
22.37
72
MIPI_CSI1_L0N
23.71
-0.32
73
MIPI_CSI1_L0P
23.39
5.2.5
USB
90 Ω differential, ± 10% trace impedance
Differential data pair matching < 6 mm
External components should be located near the USB connector.
Should be routed away from sensitive circuits and signals.
If there are test points, place them on the trace to keep branches as short as possible
If USB connector is used as the charger input, USB_VBUS node must be routed to the module using
extremely wide traces or sub planes.
About the length, please refer to the inner length of module in the following table to achieve the above
requirements:
Table 22:
Line length of USB inside the module
Pin
Signal
Length(mm)
Error Length
（
P-M
）
13
USB_DM
47.46
0.15
14
USB_DP
47.61
5.2.6
SD
Protect other sensitive signals/circuits from SDC corruption.
Protect SDC signals from noisy signals (clocks, SMPS, etc.).
Up to 200 MHz clock rate
50 Ω nominal, ±10% trace impedance
CLK to DATA/CMD length matching < 1 mm
30–35 Ω termination resistor on clock lines near the module