Sundance Spas PXIe-700, Руководство пользователя

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PXIe-700 User Guide
Page 16
Rev. 1.7
Sundance Digital Signal Processing Inc.
4790 Caughlin Parkway 233, Reno, NV 89519-0907, U.S.A.
Tel: +1 (775) 827-3103, Fax: +1 (775) 827-3664, email: sales@sundancedsp.com
www.sundancedsp.com © Sundance Digital Signal Processing Inc 2016.
4.1.5 LEDS
Note: Pins are connected to 2.5v bank
PXIe 700 LED Pinout
S.No LED FPGA Pin
1 D2 H29
2 D3 L26
3 D4 L27
4 D5 M27
5 D6 N27
Table 10 - LEDs Pinout
4.1.6 Clocks
Note: Pins are connected to 2.5v bank
PXIe 700 Clock Pinout
S.No Pin_name FPGA Pin Clock Frequency
1 FPGA_EMCCLK R24 66 MHz
2 FPGA_VCXO_CLK L25 20 MHz
3 MGT_S C8 125 MHz
4 MGT_SYS_CLK0- C7 125 MHz
5 MGT_S L8 125 MHz
6 MGT_SYS_CLK1- L7 125 MHz
7 FPGA_ K28 125 MHz
8 FPGA_SYS_CLK- K29 125 MHz
Table 11 - Clocks pinout
4.1.7 DDR3 Interface
PXIe_700 DDR3 Pinout Bank 1
Signal FPGA Pin Signal FPGA Pin
A0 AD8 CLK+ AB9
A1 AC10 CLK- AC9
A2 AB10 DQ0 AD3
A3 AB13 DQ1 AC2
A4 AA13 DQ2 AC1
A5 AA10 DQ3 AC5
A6 AA1 DQ4 AC4
A7 Y10 DQ5 AD6
A8 Y11 DQ6 AE6