Sundance Spas PXIe-700, Руководство пользователя

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PXIe-700 User Guide
Page 13
Rev. 1.7
Sundance Digital Signal Processing Inc.
4790 Caughlin Parkway 233, Reno, NV 89519-0907, U.S.A.
Tel: +1 (775) 827-3103, Fax: +1 (775) 827-3664, email: sales@sundancedsp.com
www.sundancedsp.com © Sundance Digital Signal Processing Inc 2016.
PIN G
FPGA_PIN
Rev 3.0
FPGA_PIN
Rev 4.0 H
FPGA_PIN
Rev 3.0
FPGA_PIN
Rev 4.0 I
1 PXIe AF15 AF15 PXIe_DSTARC- AG14 AG14 GND
2 PXIe AJ19 AF17 PXIe_DSTARA- AK19 AG17 GND
3 RSV RSV GND
4 U8 U8 1REFCLK- U7 U7 GND
5 1PETP1 V2 V2 1PETN1 V1 V1 GND
6 1PERP1 Y6 Y6 1PERN1 Y5 Y5 GND
7 1PETP4 1PETN4 GND
8 1PERP4 1PERN4 GND
9 1PETP7 1PETN7 GND
10 1PERP7 1PERN7 GND
Table 5 - PXIe-700 J2 Pinout
J3:
214443 from ERNI backplane connector. This is used to provide PXI control signals.
Note: These signals are connected to 1.8v Bank
PIN A FPGA_PIN B FPGA_PIN C FPGA_PIN
1 GA4 AB17 GA3 AC19 GA2 AB19
2 5v_AUX GND SYS_EN
3 12v 12V GND
4 GND GND 3.3V
5 PXI_TRIG3 AB15 PXI_TRIG4 AC16 PXI_TRIG5 AC15
6 PXI_TRIG2 AA15 GND ATNLED Y16
7 PXI_TRIG1 AE15 PXI_TRIG0 AC17 ATNSW# AA16
8 RSV GND RSV
PIN D FPGA_PIN E FPGA_PIN F FPGA_PIN
1 GA1 AB18 GA0 AA18
2 WAKE ALERT# AG19
3 GND GND GND
4 3.3V 3.3V GND
5 GND PXI_TRIG6 AC14 GND
6 PXI_STAR AA17 PXI_CLK10 AF18 GND
7 GND PXI_TRIG7 AD14
8 PXI_LBL6 AK18 PXI_LBR6 AJ18
Table 6 - PXIe-700 J2 pinout