Sun Microsystems Ultra 5, Руководство по обслуживанию

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Appendix C Functional Description C-5
C.1.2.2 Secondary PCI Buses
The secondary PCI buses are designated as PCI bus A and PCI bus B.
Bus A is a 33-MHz, 32-bit bus that interfaces between the APB ASIC and the PCI
slots, with no motherboard device communications. PCI bus A is a 5-VDC-only bus
and the only supported boards are 5-VDC type.
PCI bus B is also a 33-MHz, 32-bit bus. Unlike PCI bus A, PCI bus B does not
interface to any PCI slots; however, it does communicate with motherboard devices.
The motherboard devices residing on PCI bus B include:
■
APB ASIC
■
PCIO ASIC
■
PCI-based graphics controller
■
PCI-IDE interface
C.1.2.3 APB ASIC
Refer to Section C.1.5.1 “APB” on page C-19.
C.1.2.4 PCIO ASIC
Refer to Section C.1.5.2 “PCIO” on page C-20.
C.1.2.5 10-/100-Mbit Ethernet
The Ethernet channel engine within the PCIO ASIC provides a buffered full-duplex
DMA engine and a media access controller (MAC) function. The descriptor-based
DMA engine contains independent transmit and receive channels, each with 2
Kbytes of on-chip buffering. The MAC provides a 10-Mbps or a 100-Mbps
CSMA/CD protocol based upon a network interface conforming to IEEE 802.3,
proposed IEEE 802.30, and Ethernet specifications. The following figure shows a
functional block diagram of the 10-/100-Mbit Ethernet.