Stollmann BlueMod+S/AI, Справочник по аппаратуре

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S/AI
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5.5.2 EXT-RES#
Input EXT-RES# has a Schmitt-Trigger characteristic and an internal pull-up resistor.
T
amb
= 25°C
Symbol Item Condition Limit Unit
Min Typ Max
V
IL
Low-Level Threshold VSUP = 1,8 to 3,6V 0,34*VSUP V
V
IH
High-Level Threshold VSUP = 1,8 to 3,6V 0,62*VSUP V
V
HYST
Hysteresis VSUP = 3,0V 800 mV
R
PU
pull-up resistor 11 13 16 k
Ω
C
l
Input Capacitance 2,5 pF
Table 12: DC Characteristics, EXT-RES#
5.5.3 External Slow Clock SLCK
The following table is applicable if an external slow clock signal is fed into XL-IN/SLCK. This may
be a square wave, a clipped sine wave, a sine wave or a rail-to-rail digital signal. Frequency must
be 32,/-250ppm (refer to 3.9). DC offset is not an issue as long as the input voltage is
between VSS and VSUP at all times. Firmware will detect presence of external slow clock signal at
startup; signal has to stay active as long as the S is powered.
T
amb
= 25°C
Symbol Item Condition Limit Unit
Min Typ Max
V
SLCKL
Low-Level Input Voltage VSUP = 1,8 to 3,6V 0,0
-
VSUP-V
SLCK
V
V
SLCKH
High-Level Input Voltage VSUP = 1,8 to 3,6V
VSUP-V
SLCK
-
VSUP V
V
SLCK
(1)
Amplitude (peak_peak) VSUP = 1,8 to 3,6V 0,2
-
VSUP V
C
l
Input Capacitance
4
pF
(1)
input voltage required between VSS and VSUP at all times
Table 13: DC Characteristics, SLCK