STM32F42xx and STM32F43xx silicon limitations
STM32F42xx and STM32F43xx
DocID023833 Rev 5
However, if the TxFIFO read controller receives the TxFIFO flush command exactly one
clock cycle after receiving the status from the MAC, the controller remains stuck in the Idle
state and stops transmitting frames from the TxFIFO. The system can recover from this
state only with a reset (e.g. a soft reset).
Workaround
Do not use the TxFIFO flush feature.
If TXFIFO flush is really needed, wait until the TxFIFO is empty prior to using the TxFIFO
flush command.
2.7.4
Transmit frame data corruption
Frame data corrupted when the TxFIFO is repeatedly transitioning from non-empty to empty
and then back to non-empty.
Description
Frame data may get corrupted when the TxFIFO is repeatedly transitioning from non-empty
to empty for a very short period, and then from empty to non-empty, without causing an
underflow.
This transitioning from non-empty to empty and back to non-empty happens when the rate
at which the data is being written to the TxFIFO is almost equal to or a little less than the
rate at which the data is being read.
This corruption cannot be detected by the receiver when the CRC is inserted by the MAC,
as the corrupted data is used for the CRC computation.
Workaround
Use the Store-and-Forward mode: TSF=1 (bit 21 in ETH_DMAOMR). In this mode, the data
is transmitted only when the whole packet is available in the TxFIFO.
2.7.5
Successive write operations to the same register might not be fully
taken into account
Description
A write to a register might not be fully taken into account if a previous write to the same
register is performed within a time period of four TX_CLK/RX_CLK clock cycles. When this
error occurs, reading the register returns the most recently written value, but the Ethernet
MAC continues to operate as if the latest write operation never occurred.
Table 5: Impacted registers and bits
for the registers and bits impacted by this limitation.