STMicroelectronics STM32F427 Скачать руководство пользователя страница 19 | Manualshive

Страница: 19 / 36

STMicroelectronics STM32F427 Скачать руководство пользователя страница 19

DocID023833 Rev 5

STM32F42xx and STM32F43xx

STM32F42xx and STM32F43xx silicon limitations

35

2.7

Ethernet peripheral limitations

2.7.1

Incorrect layer 3 (L3) checksum is inserted in transmitted IPv6 packets
without TCP, UDP or ICMP payloads

Description

The application provides the per-frame control to instruct the MAC to insert the L3
checksums for TCP, UDP and ICMP packets. When automatic checksum insertion is
enabled and the input packet is an IPv6 packet without the TCP, UDP or ICMP payload, then
the MAC may incorrectly insert a checksum into the packet. For IPv6 packets without a TCP,
UDP or ICMP payload, the MAC core considers the next header (NH) field as the extension
header and continues to parse the extension header. Sometimes, the payload data in such
packets matches the NH field for TCP, UDP or ICMP and, as a result, the MAC core inserts
a checksum.

Workaround

When the IPv6 packets have a TCP, UDP or ICMP payload, enable checksum insertion for
transmit frames, or bypass checksum insertion by using the CIC (checksum insertion
control) bits in TDES0 (bits 23:22).

2.7.2 The

Ethernet

MAC

processes invalid extension headers in the received

IPv6 frames

Description

In IPv6 frames, there can be zero or some extension headers preceding the actual IP
payload. The Ethernet MAC processes the following extension headers defined in the IPv6
protocol: Hop-by-Hop Options header, Routing header and Destination Options header.
All extension headers, except the Hop-by-Hop extension header, can be present multiple
times and in any order before the actual IP payload. The Hop-by-Hop extension header, if
present, has to come immediately after the IPv6’s main header.

The Ethernet MAC processes all (valid or invalid) extension headers including the Hop-by-
Hop extension headers that are present after the first extension header. For this reason, the
GMAC core will accept IPv6 frames with invalid Hop-by-Hop extension headers. As a
consequence, it will accept any IP payload as valid IPv6 frames with TCP, UDP or ICMP
payload, and then incorrectly update the Receive status of the corresponding frame.

Workaround

None.

2.7.3

MAC stuck in the Idle state on receiving the TxFIFO flush command
exactly 1 clock cycle after a transmission completes

Description

When the software issues a TxFIFO flush command, the transfer of frame data stops (even
in the middle of a frame transfer). The TxFIFO read controller goes into the Idle state
(TFRS=00 in ETH_MACDBGR) and then resumes its normal operation.

«
...
17
18
19
20
21
...
»

Содержание STM32F427

Страница 1: ...1 1 The REV_ID bits in the DBGMCU_IDCODE register show the revision code of the device see the RM0090 STM32F4xx reference manual for details on how to find the revision code Order code Revision code m...

Страница 2: ...ral limitation 13 2 2 1 RVU and PVU flags are not reset in STOP mode 13 2 3 I2C peripheral limitations 13 2 3 1 SMBus standard not fully supported 13 2 3 2 Start cannot be generated after a misplaced...

Страница 3: ...uccessive write operations to the same register might not be fully taken into account 20 2 8 FMC peripheral limitation 23 2 8 1 Dummy read cycles inserted when reading synchronous memories 23 2 8 2 FM...

Страница 4: ...Contents STM32F42xx and STM32F43xx 4 36 DocID023833 Rev 5 2 11 2 DMA request not automatically cleared by DMAEN 0 27 Appendix A Revision code on device marking 29 Revision history 35...

Страница 5: ...List of tables Table 1 Device identification 1 Table 2 Device summary 1 Table 3 Cortex M4 core limitations and impact on microcontroller behavior 7 Table 4 Summary of silicon limitations 8 Table 5 Im...

Страница 6: ...f figures Figure 1 TFBGA216 top package view 29 Figure 2 WLCSP143 top package view 30 Figure 3 LQFP208 top package view 30 Figure 4 UFBGA176 top package view 31 Figure 5 LQFP176 top package view 32 Fi...

Страница 7: ...rrupt results in the load instruction being executed an additional time For all the instructions performing an update of the base register the base register is erroneously updated on each execution re...

Страница 8: ...attribute to RTC and IWDG registers could be managed incorrectly A A Section 2 1 6 Delay after an RCC peripheral clock enabling A A Section 2 1 7 Internal noise impacting the ADC accuracy A A Section...

Страница 9: ...ripheral limitations Section 2 7 1 Incorrect layer 3 L3 checksum is inserted in transmitted IPv6 packets without TCP UDP or ICMP payloads A A Section 2 7 2 The Ethernet MAC processes invalid extension...

Страница 10: ...only Stop debug mode with WFE entry Workaround To debug Stop mode with WFE entry the WFE instruction must be inside a dedicated function with 1 instruction NOP between the execution of the WFE and th...

Страница 11: ...consequence the MCU might not be able to wake up from Standby mode Workaround To avoid this problem the following sequence should be applied before entering Standby mode Disable all used wakeup sourc...

Страница 12: ...This delay depends on the peripheral s mapping If the peripheral is mapped on AHB the delay should be equal to 2 AHB cycles If the peripheral is mapped on APB the delay should be equal to 1 AHB APB p...

Страница 13: ...he IWDG_RLR or the IWDG_PR register the application software must wait for the RVU or PVU flag to be reset However since the RVU PVU bit is not reset after exiting the Stop mode the software goes into...

Страница 14: ...n can occur only in the following configuration in Master mode in Standard mode at a frequency between 88 kHz and 100 kHz no limitation in Fast mode SCL rise time If the slave does not stretch the clo...

Страница 15: ...SCL signals within the maximum timing tr which is 300 ns in fast mode and 1000 ns in Standard mode The rise time tr is measured from VIL and VIH with levels set at 0 3VDD_I2C and 0 7VDD_I2C Workaround...

Страница 16: ...gister Description In full duplex mode when the Parity Error flag is set by the receiver at the end of a reception it may be cleared while transmitting by reading the USART_SR register to check the TX...

Страница 17: ...und Workarounds are required only if the other USART device violates the communication protocol which is not the case in most applications Two workarounds can be used After data reception and before r...

Страница 18: ...e In this way the host application which intends to supports only IN traffic also has to allocate some space for the TxFIFO Since a USB host is expected to support any kind of connected endpoint it is...

Страница 19: ...he received IPv6 frames Description In IPv6 frames there can be zero or some extension headers preceding the actual IP payload The Ethernet MAC processes the following extension headers defined in the...

Страница 20: ...sing an underflow This transitioning from non empty to empty and back to non empty happens when the rate at which the data is being written to the TxFIFO is almost equal to or a little less than the r...

Страница 21: ..._DMABMR 7 EDFE ETH_DMAOMR 26 DTCEFD 25 RSF 20 FTF 7 FEF 6 FUGF 4 3 RTC GMAC registers ETH_MACCR 25 CSTF 23 WD 22 JD 19 17 IFG 16 CSD 14 FES 13 ROD 12 LM 11 DM 10 IPCO 9 RD 7 APCS 6 5 BL 4 DC 3 TE 2 RE...

Страница 22: ...1HR MAC address 1 high register ETH_MACA1LR MAC address 1 low register ETH_MACA2HR MAC address 2 high register ETH_MACA2LR MAC address 2 low register ETH_MACA3HR MAC address 3 high register ETH_MACA3L...

Страница 23: ...st access However the extra data values which are read are not used by the FMC and there is no functional failure Workaround None 2 8 2 FMC synchronous mode and NWAIT signal disabled Description When...

Страница 24: ...bus is 16 bit or 8 bit wide 32 bit SDRAM mode is not affected RBURST bit is reset in the FMC_SDCR1 register read FIFO disabled An interrupt occurs while CPU is performing an AHB incrementing bursts re...

Страница 25: ...KCR register to 1 glitches can occur on the SDIOCLK output clock resulting in wrong data to be written into the SD MMC card or into the SDIO device As a consequence a CRC error will be reported to the...

Страница 26: ...in SDIO_DCTRL register and TXFIFOE 0 in SDIO_STA register As a consequence the write transfer fails and the data lines are corrupted Workaround After sending the write command RW_MULTIPLE_REGISTER or...

Страница 27: ...peripheral limitations 2 11 1 DMA underrun flag management Description If the DMA is not fast enough to input the next digital data to the DAC as a consequence the same digital data is converted twic...

Страница 28: ...23833 Rev 5 Workaround To stop the current DMA to DAC transfer and restart the following sequence should be applied 1 Check if DMAUDR is set 2 Clear the DAC DMAEN bit 3 Clear the EN bit of the DAC DMA...

Страница 29: ...6 Figure 7 show the marking compositions for the TFBGA216 WLCSP143 LQFP208 UFBGA176 LQFP176 LQFP144 and LQFP100 packages respectively The only fields shown are the Additional field containing the rev...

Страница 30: ...DocID023833 Rev 5 Figure 2 WLCSP143 top package view Figure 3 LQFP208 top package view MS32786V1 Additional information field including Revision code Date code Year Week Year Week 3 6 7EEK 9EAR ATE CO...

Страница 31: ...DocID023833 Rev 5 31 36 STM32F42xx and STM32F43xx Revision code on device marking 35 Figure 4 UFBGA176 top package view 3 6 DDITIONAL INFORMATION FIELD INCLUDING REVISION CODE 7EEK 9EAR 34 LOGO...

Страница 32: ...Revision code on device marking STM32F42xx and STM32F43xx 32 36 DocID023833 Rev 5 Figure 5 LQFP176 top package view AI 7EEK 9EAR ATE CODE 9EAR 7EEK...

Страница 33: ...cID023833 Rev 5 33 36 STM32F42xx and STM32F43xx Revision code on device marking 35 Figure 6 LQFP144 top package view DDITIONAL INFORMATION FIELD INCLUDING 2EVISION CODE AI B 7EEK 9EAR ATE CODE 9EAR 7E...

Страница 34: ...evision code on device marking STM32F42xx and STM32F43xx 34 36 DocID023833 Rev 5 Figure 7 LQFP100 top package view DDITIONAL INFORMATION FIELD INCLUDING 2EVISION CODE AI B 7EEK 9EAR ATE CODE 9EAR 7EEK...

Страница 35: ...a transmission 19 Sep 2013 4 Added STM32F429xx and STM32F439xx devices Removed FSMC limitations Added Section 2 3 5 Both SDA and SCL maximum rise time tr violated when VDD_I2C bus higher than VDD 0 3...

Страница 36: ...PATENT COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT ST PRODUCTS ARE NOT DESIGNED OR AUTHORIZED FOR USE IN A SAFETY CRITICAL APPLICATIONS SUCH AS LIFE SUPPORTING ACTIVE IMPLANTED DEVICES OR SYSTEMS W...

Отзывы:

Нет отзывов