DocID023833 Rev 5
STM32F42xx and STM32F43xx
STM32F42xx and STM32F43xx silicon limitations
35
Workaround
If the master device allows it, use the clock stretching mechanism by programming the bit
NOSTRETCH=0 in the I2C_CR1 register.
If the master device does not allow it, ensure that the software is fast enough when polling
the TXE or ADDR flag to immediately write to the DR data register. For instance, use an
interrupt on the TXE or ADDR flag and boost its priority to the higher level.
2.3.5
Both SDA and SCL maximum rise time (t
r
) violated when VDD_I2C bus
higher than ((VDD+0.3) / 0.7) V
Description
When an external legacy I
2
C bus voltage (VDD_I2C) is set to 5 V while the MCU is powered
from V
DD
, the internal 5-Volt tolerant circuitry is activated as soon the input voltage (V
IN
)
reaches the V
DD
+ diode threshold level. An additional internal large capacitance then
prevents the external pull-up resistor (R
P
) from rising the SDA and SCL signals within the
maximum timing (t
r
) which is 300 ns in fast mode and 1000 ns in Standard mode.
The rise time (t
r
) is measured from V
IL
and V
IH
with levels set at 0.3VDD_I2C and
0.7VDD_I2C.
Workaround
The external VDD_I2C bus voltage should be limited to a maximum value of
((VDD+0.3) / 0.7) V. As a result, when the MCU is powered from V
DD
=3.3 V, VDD_I2C
should not exceed 5.14 V to be compliant with I
2
C specifications.
2.4
I2S peripheral limitation
2.4.1
In I2S slave mode, WS level must be set by the external master
when enabling the I2S
Description
In slave mode, the WS signal level is used only to start the communication. If the I2S (in
slave mode) is enabled while the master is already sending the clock and the WS signal
level is low (for I2S protocol) or is high (for the LSB or MSB-justified mode), the slave starts
communicating data immediately. In this case, the master and slave will be desynchronized
throughout the whole communication.
Workaround
The I2S peripheral must be enabled when the external master sets the WS line at:
•
High level when the I2S protocol is selected.
•
Low level when the LSB or MSB-justified mode is selected.
