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Reset and clock control for STM32F405xx/07xx and STM32F415xx/17xx(RCC)

RM0090

DocID018909 Rev 11

7.3.22

RCC clock control & status register (RCC_CSR)

Address offset: 0x74

Reset value: 0x0E00 0000, reset by system reset, except reset flags by power reset only.

Access: 0

≤

wait state

≤

3, word, half-word and byte access

Wait states are inserted in case of successive accesses to this register.

Bit 2

LSEBYP:

External low-speed oscillator bypass

Set and cleared by software to bypass the oscillator. This bit can be written only when the
LSE clock is disabled.
0: LSE oscillator not bypassed
1: LSE oscillator bypassed

Bit 1

LSERDY:

External low-speed oscillator ready

Set and cleared by hardware to indicate when the external 32 kHz oscillator is stable. After
the LSEON bit is cleared, LSERDY goes low after 6 external low-speed oscillator clock
cycles.
0: LSE clock not ready
1: LSE clock ready

Bit 0

LSEON:

External low-speed oscillator enable

Set and cleared by software.
0: LSE clock OFF
1: LSE clock ON

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

LPWR

RSTF

WWDG

RSTF

IWDG

RSTF

SFT

RSTF

POR

RSTF

PIN

RSTF

BORRS

TF

RMVF

Reserved

r

r

r

r

r

r

r

rt_w

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Reserved

LSIRDY LSION

r

rw

Bit 31

LPWRRSTF:

Low-power reset flag

Set by hardware when a Low-power management reset occurs.
Cleared by writing to the RMVF bit.
0: No Low-power management reset occurred
1: Low-power management reset occurred
For further information on Low-power management reset, refer to

Low-power management

.

Bit 30

WWDGRSTF:

Window watchdog reset flag

Set by hardware when a window watchdog reset occurs.
Cleared by writing to the RMVF bit.
0: No window watchdog reset occurred
1: Window watchdog reset occurred

Bit 29

IWDGRSTF

: Independent watchdog reset flag

Set by hardware when an independent watchdog reset from V

DD

domain occurs.

Cleared by writing to the RMVF bit.
0: No watchdog reset occurred
1: Watchdog reset occurred

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Содержание STM32F405

Страница 1: ...2F42xxx and STM32F43xxx constitute a family of microcontrollers with different memory sizes packages and peripherals For ordering information mechanical and electrical device characteristics please re...

Страница 2: ...HS DMA bus 63 2 1 8 LCD TFT controller DMA bus 63 2 1 9 DMA2D bus 63 2 1 10 BusMatrix 63 2 1 11 AHB APB bridges APB 64 2 2 Memory organization 64 2 3 Memory map 64 2 3 1 Embedded SRAM 68 2 3 2 Flash...

Страница 3: ...x 07xx and STM32F415xx 17xx 98 3 9 2 Flash access control register FLASH_ACR for STM32F42xxx and STM32F43xxx 99 3 9 3 Flash key register FLASH_KEYR 100 3 9 4 Flash option key register FLASH_OPTKEYR 10...

Страница 4: ...R 125 5 2 3 Programmable voltage detector PVD 125 5 3 Low power modes 126 5 3 1 Slowing down system clocks 128 5 3 2 Peripheral clock gating 128 5 3 3 Sleep mode 129 5 3 4 Stop mode STM32F405xx 07xx a...

Страница 5: ...RCC PLL configuration register RCC_PLLCFGR 163 6 3 3 RCC clock configuration register RCC_CFGR 165 6 3 4 RCC clock interrupt register RCC_CIR 167 6 3 5 RCC AHB1 peripheral reset register RCC_AHB1RSTR...

Страница 6: ...RCC PLL configuration register RCC_PLLSAICFGR 206 6 3 25 RCC Dedicated Clock Configuration Register RCC_DCKCFGR 207 6 3 26 RCC register map 210 7 Reset and clock control for STM32F405xx 07xx and STM3...

Страница 7: ...clock enable in low power mode register RCC_AHB1LPENR 252 7 3 17 RCC AHB2 peripheral clock enable in low power mode register RCC_AHB2LPENR 254 7 3 18 RCC AHB3 peripheral clock enable in low power mode...

Страница 8: ..._PUPDR x A I J K 284 8 4 5 GPIO port input data register GPIOx_IDR x A I J K 285 8 4 6 GPIO port output data register GPIOx_ODR x A I J K 285 8 4 7 GPIO port bit set reset register GPIOx_BSRR x A I J...

Страница 9: ...egister 3 SYSCFG_EXTICR3 300 9 3 6 SYSCFG external interrupt configuration register 4 SYSCFG_EXTICR4 301 9 3 7 Compensation cell control register SYSCFG_CMPCR 302 9 3 8 SYSCFG register maps for STM32F...

Страница 10: ...DMA_SxM0AR x 0 7 334 10 5 9 DMA stream x memory 1 address register DMA_SxM1AR x 0 7 334 10 5 10 DMA stream x FIFO control register DMA_SxFCR x 0 7 335 10 5 11 DMA register map 337 11 Chrom Art Accele...

Страница 11: ...emory address register DMA2D_FGCMAR 365 11 5 13 DMA2D background CLUT memory address register DMA2D_BGCMAR 366 11 5 14 DMA2D output PFC control register DMA2D_OPFCCR 366 11 5 15 DMA2D output color reg...

Страница 12: ...393 13 3 3 Channel selection 393 13 3 4 Single conversion mode 394 13 3 5 Continuous conversion mode 395 13 3 6 Timing diagram 395 13 3 7 Analog watchdog 395 13 3 8 Scan mode 396 13 3 9 Injected chan...

Страница 13: ...ster ADC_LTR 425 13 13 9 ADC regular sequence register 1 ADC_SQR1 425 13 13 10 ADC regular sequence register 2 ADC_SQR2 426 13 13 11 ADC regular sequence register 3 ADC_SQR3 426 13 13 12 ADC injected...

Страница 14: ...ion 446 14 5 DAC registers 447 14 5 1 DAC control register DAC_CR 447 14 5 2 DAC software trigger register DAC_SWTRIGR 450 14 5 3 DAC channel1 12 bit right aligned data holding register DAC_DHR12R1 45...

Страница 15: ...CMI interrupts 467 15 8 DCMI register description 468 15 8 1 DCMI control register 1 DCMI_CR 468 15 8 2 DCMI status register DCMI_SR 470 15 8 3 DCMI raw interrupt status register DCMI_RIS 471 15 8 4 D...

Страница 16: ...6 7 8 LTDC Interrupt Enable Register LTDC_IER 496 16 7 9 LTDC Interrupt Status Register LTDC_ISR 497 16 7 10 LTDC Interrupt Clear Register LTDC_ICR 497 16 7 11 LTDC Line Interrupt Position Configurati...

Страница 17: ...6 17 3 3 Repetition counter 524 17 3 4 Clock selection 526 17 3 5 Capture compare channels 528 17 3 6 Input capture mode 530 17 3 7 PWM input mode 532 17 3 8 Forced output mode 533 17 3 9 Output compa...

Страница 18: ...compare register 2 TIMx_CCR2 575 17 4 16 TIM1 TIM8 capture compare register 3 TIMx_CCR3 575 17 4 17 TIM1 TIM8 capture compare register 4 TIMx_CCR4 576 17 4 18 TIM1 TIM8 break and dead time register T...

Страница 19: ...Mx prescaler TIMx_PSC 633 18 4 12 TIMx auto reload register TIMx_ARR 633 18 4 13 TIMx capture compare register 1 TIMx_CCR1 634 18 4 14 TIMx capture compare register 2 TIMx_CCR2 634 18 4 15 TIMx captur...

Страница 20: ...nter TIMx_CNT 673 19 4 9 TIM9 12 prescaler TIMx_PSC 673 19 4 10 TIM9 12 auto reload register TIMx_ARR 673 19 4 11 TIM9 12 capture compare register 1 TIMx_CCR1 674 19 4 12 TIM9 12 capture compare regis...

Страница 21: ...6 20 4 5 TIM6 TIM7 event generation register TIMx_EGR 696 20 4 6 TIM6 TIM7 counter TIMx_CNT 696 20 4 7 TIM6 TIM7 prescaler TIMx_PSC 697 20 4 8 TIM6 TIM7 auto reload register TIMx_ARR 697 20 4 9 TIM6 T...

Страница 22: ...an encryption or a decryption 735 23 3 7 Context swapping 736 23 4 CRYP interrupts 738 23 5 CRYP DMA interface 739 23 6 CRYP registers 739 23 6 1 CRYP control register CRYP_CR for STM32F415 417xx 739...

Страница 23: ...H functional description 764 25 3 1 Duration of the processing 766 25 3 2 Data type 766 25 3 3 Message digest computing 768 25 3 4 Message padding 769 25 3 5 Hash operation 770 25 3 6 HMAC operation 7...

Страница 24: ...mp function 801 26 3 13 Tamper detection 802 26 3 14 Calibration clock output 803 26 3 15 Alarm output 804 26 4 RTC and low power modes 804 26 5 RTC interrupts 805 26 6 RTC registers 806 26 6 1 RTC ti...

Страница 25: ...ption 830 27 3 1 Mode selection 830 27 3 2 I2C slave mode 833 27 3 3 I2C master mode 836 27 3 4 Error conditions 842 27 3 5 Programmable noise filter 843 27 3 6 SDA SCL line control 844 27 3 7 SMBus 8...

Страница 26: ...addressing 887 28 3 10 Error flags 889 28 3 11 SPI interrupts 890 28 4 I2 S functional description 891 28 4 1 I2 S general description 891 28 4 2 I2S full duplex 892 28 4 3 Supported audio protocols...

Страница 27: ...925 29 7 4 Frame synchronization offset 925 29 7 5 FS signal role 925 29 8 Slot configuration 926 29 9 SAI clock generator 928 29 10 Internal FIFOs 929 29 11 AC 97 link controller 932 29 12 Specific...

Страница 28: ...nsmitter USART 958 30 1 USART introduction 958 30 2 USART main features 958 30 3 USART functional description 959 30 3 1 USART character description 962 30 3 2 Transmitter 963 30 3 3 Receiver 966 30 3...

Страница 29: ...rating voltage range validation 1026 31 4 4 Card identification process 1027 31 4 5 Block write 1028 31 4 6 Block read 1029 31 4 7 Stream access stream write and stream read MultiMediaCard only 1029 3...

Страница 30: ...55 31 9 5 SDIO command response register SDIO_RESPCMD 1056 31 9 6 SDIO response 1 4 register SDIO_RESPx 1056 31 9 7 SDIO data timer register SDIO_DTIMER 1057 31 9 8 SDIO data length register SDIO_DLEN...

Страница 31: ...7 5 Message storage 1082 32 7 6 Error management 1084 32 7 7 Bit timing 1084 32 8 bxCAN interrupts 1086 32 9 CAN registers 1088 32 9 1 Register access protection 1088 32 9 2 CAN control and status reg...

Страница 32: ...nitialization of a transfer using DMA 1156 33 6 2 Host bus burst access 1156 33 6 3 Host data buffer alignment 1157 33 6 4 Buffer size calculations 1157 33 6 5 DMA arbiter 1158 33 6 6 Error response t...

Страница 33: ...USB host states 1243 34 6 3 Host channels 1245 34 6 4 Host scheduler 1246 34 7 SOF trigger 1247 34 7 1 Host SOFs 1247 34 7 2 Peripheral SOFs 1248 34 8 Power options 1248 34 9 Dynamic update of the OTG...

Страница 34: ...1362 35 USB on the go high speed OTG_HS 1369 35 1 OTG_HS introduction 1369 35 2 OTG_HS main features 1369 35 2 1 General features 1370 35 2 2 Host mode features 1371 35 2 3 Peripheral mode features 13...

Страница 35: ...rs 1418 35 12 4 Device mode registers 1430 35 12 5 OTG_HS power and clock gating control register OTG_HS_PCGCCTL 1458 35 12 6 OTG_HS register map 1458 35 13 OTG_HS programming model 1473 35 13 1 Core...

Страница 36: ...Flash pre wait functionality 1576 36 6 6 Computation of the error correction code ECC in NAND Flash memory 1577 36 6 7 PC Card CompactFlash operations 1578 36 6 8 NAND Flash PC Card control registers...

Страница 37: ...SDRAM controller functional description 1651 37 7 4 Low power modes 1657 37 7 5 SDRAM controller registers 1661 37 8 FMC register map 1667 38 Debug support DBG 1670 38 1 Overview 1670 38 2 Reference A...

Страница 38: ...Embedded trace macrocell 1689 38 15 1 General description 1689 38 15 2 Signal protocol packet types 1689 38 15 3 Main ETM registers 1689 38 15 4 Configuration example 1690 38 16 MCU debug component DB...

Страница 39: ...39 1731 RM0090 Contents 39 38 17 10 Example of configuration 1700 38 18 DBG register map 1700 39 Device electronic signature 1702 39 1 Unique device ID register 96 bits 1702 39 2 Flash size 1703 40 Re...

Страница 40: ...the option bytes STM32F42xxx and STM32F43xxx 90 Table 17 Access versus read protection level 94 Table 18 OTP area organization 97 Table 19 Flash register map and reset values STM32F405xx 07xx and STM3...

Страница 41: ...ontroller register map and reset values 389 Table 64 External interrupt event controller register map and reset values 389 Table 65 ADC pins 393 Table 66 Analog watchdog channel selection 396 Table 67...

Страница 42: ...es 731 Table 113 CRYP register map and reset values for STM32F415 417xx 754 Table 114 CRYP register map and reset values for STM32F43xxx 755 Table 115 RNG register map and reset map 762 Table 116 HASH...

Страница 43: ...values 1010 Table 149 SDIO I O definitions 1015 Table 150 Command format 1019 Table 151 Short response format 1020 Table 152 Long response format 1020 Table 153 Command path status flags 1020 Table 15...

Страница 44: ...egisters CSRs 1389 Table 204 Host mode control and status registers CSRs 1390 Table 205 Device mode control and status registers 1391 Table 206 Data FIFO DFIFO access register map 1393 Table 207 Power...

Страница 45: ...address mapping with 16 bit data bus width 1598 Table 257 SDRAM address mapping with 32 bit data bus width 1598 Table 258 Programmable NOR PSRAM access parameters 1600 Table 259 Non multiplexed I O NO...

Страница 46: ...gisters 1678 Table 296 32 bit debug port registers addressed through the shifted value A 3 2 1679 Table 297 Packet request 8 bits 1680 Table 298 ACK response 3 bits 1681 Table 299 DATA transfer 33 bit...

Страница 47: ...uit 214 Figure 21 Clock tree 216 Figure 22 HSE LSE clock sources 218 Figure 23 Frequency measurement with TIM5 in Input capture mode 223 Figure 24 Frequency measurement with TIM11 in Input capture mod...

Страница 48: ...ster calculation algorithm 441 Figure 69 DAC conversion SW trigger enabled with LFSR wave generation 441 Figure 70 DAC triangle wave generation 442 Figure 71 DAC conversion SW trigger enabled with tri...

Страница 49: ...ementary output with dead time insertion 538 Figure 121 Dead time waveforms with delay greater than the negative pulse 538 Figure 122 Dead time waveforms with delay greater than the positive pulse 538...

Страница 50: ...ircuit in gated mode 611 Figure 172 Control circuit in trigger mode 611 Figure 173 Control circuit in external clock mode 2 trigger mode 612 Figure 174 Master Slave timer example 613 Figure 175 Gating...

Страница 51: ...e 218 DES TDES ECB mode encryption 716 Figure 219 DES TDES ECB mode decryption 716 Figure 220 DES TDES CBC mode encryption 718 Figure 221 DES TDES CBC mode decryption 719 Figure 222 AES ECB mode encry...

Страница 52: ...895 Figure 267 Receiving 0x8EAA33 895 Figure 268 I2 S Philips standard 16 bit extended to 32 bit packet frame with CPOL 0 895 Figure 269 Example 896 Figure 270 MSB Justified 16 bit or 32 bit full acc...

Страница 53: ...rmal mode 993 Figure 315 Transmission using DMA 995 Figure 316 Reception using DMA 996 Figure 317 Hardware flow control between 2 USARTs 996 Figure 318 RTS flow control 997 Figure 319 CTS flow control...

Страница 54: ...71 Wakeup frame filter register 1147 Figure 372 Networked time synchronization 1150 Figure 373 System time update using the Fine correction method 1152 Figure 374 PTP trigger output to TIM2 ITR1 conne...

Страница 55: ...igure 419 Bulk control IN transactions Slave mode 1485 Figure 420 Normal interrupt OUT IN transactions DMA mode 1487 Figure 421 Normal interrupt OUT IN transactions Slave mode 1488 Figure 422 Normal i...

Страница 56: ...Figure 466 ModeD write access waveforms 1616 Figure 467 Muxed read access waveforms 1618 Figure 468 Muxed write access waveforms 1618 Figure 469 Asynchronous wait during a read access waveforms 1620 F...

Страница 57: ...ing 1 Writing 0 has no effect on the bit value read clear rc_w0 Software can read as well as clear this bit by writing 0 Writing 1 has no effect on the bit value read clear by read rc_r Software can r...

Страница 58: ...program is running ICP in circuit programming ICP is the ability to program the Flash memory of a microcontroller using the JTAG protocol the SWD protocol or the bootloader while the device is mounte...

Страница 59: ...bus DMA2 peripheral bus Ethernet DMA bus USB OTG HS DMA bus Seven slaves Internal Flash memory ICode bus Internal Flash memory DCode bus Main internal SRAM1 112 KB Auxiliary internal SRAM2 16 KB AHB1...

Страница 60: ...018909 Rev 11 Figure 1 System architecture for STM32F405xx 07xx and STM32F415xx 17xx devices 2 ORTEX 0 0 THERNET 53 4 3 US MATRIX 3 LASH MEMORY 32 BYTE 32 BYTE PERIPHERALS 3 3TATIC EM TL BUS BUS 3 BUS...

Страница 61: ...emory bus Eight slaves Internal Flash memory ICode bus Internal Flash memory DCode bus Main internal SRAM1 112 KB Auxiliary internal SRAM2 16 KB Auxiliary internal SRAM3 64 KB AHB1peripherals includin...

Страница 62: ...e target of this bus is a memory containing code or data internal Flash memory or external memories through the FSMC FMC 2 1 3 S bus This bus connects the system bus of the Cortex M4 with FPU core to...

Страница 63: ...AMs SRAM1 SRAM2 SRAM3 internal Flash memory and external memories through the FSMC FMC 2 1 7 USB OTG HS DMA bus This bus connects the USB OTG HS DMA master interface to the BusMatrix This bus is used...

Страница 64: ...zed within the same linear 4 Gbyte address space The bytes are coded in memory in little endian format The lowest numbered byte in a word is considered the word s least significant byte and the highes...

Страница 65: ...BKPSRAM 0x4002 3C00 0x4002 3FFF Flash interface register Section 3 9 Flash interface registers 0x4002 3800 0x4002 3BFF RCC Section 7 3 25 RCC register map on page 267 0x4002 3000 0x4002 33FF CRC Sect...

Страница 66: ...3400 0x4001 37FF SPI4 APB2 Section 28 5 10 SPI register map on page 918 0x4001 3000 0x4001 33FF SPI1 APB2 Section 28 5 10 SPI register map on page 918 0x4001 2C00 0x4001 2FFF SDIO Section 31 9 16 SDI...

Страница 67: ...4000 3C00 0x4000 3FFF SPI3 I2S3 0x4000 3800 0x4000 3BFF SPI2 I2S2 0x4000 3400 0x4000 37FF I2S2ext 0x4000 3000 0x4000 33FF IWDG Section 21 4 5 IWDG register map on page 703 0x4000 2C00 0x4000 2FFF WWDG...

Страница 68: ...remap is selected Section 9 2 1 SYSCFG memory remap register SYSCFG_MEMRMP in the SYSCFG controller To get the max performance on SRAM execution physical remap should be selected boot or software sel...

Страница 69: ...Reading address 0x22006008 returns the value 0x01 or 0x00 of bit 2 of the byte at SRAM address 0x20000300 0x01 bit set 0x00 bit reset For more information on bit banding please refer to the Cortex M4...

Страница 70: ...ash memory configuration the device boots from system memory and the boot loader jumps to execute the user application programmed in Flash memory bank 2 For further details please refer to AN2606 Note...

Страница 71: ...Flash memory Flash memory Flash memory Flash memory 0x0400 0000 0x07FF FFFF Reserved Reserved Reserved FSMC bank 1 NOR PSRAM 2 128 MB Aliased 0x0000 0000 0x000F FFFF 1 2 Flash 1 MB Aliased SRAM1 112 K...

Страница 72: ...0000 only the first two regions of bank 1 memory controller bank 1 NOR PSRAM 1 and NOR PSRAM 2 or SDRAM bank 1 can be remapped In remap mode the CPU can access the external memory via ICode bus inste...

Страница 73: ...Flash memory program erase operations Read write protections Prefetch on I Code 64 cache lines of 128 bits on I Code 8 cache lines of 128 bits on D Code Figure 3 shows the Flash memory interface conn...

Страница 74: ...memory from which the device boots in System memory boot mode 512 OTP one time programmable bytes for user data The OTP area contains 16 additional bytes used to lock the corresponding OTP data block...

Страница 75: ...0800 4000 0x0800 7FFF 16 Kbytes Sector 2 0x0800 8000 0x0800 BFFF 16 Kbytes Sector 3 0x0800 C000 0x0800 FFFF 16 Kbytes Sector 4 0x0801 0000 0x0801 FFFF 64 Kbytes Sector 5 0x0802 0000 0x0803 FFFF 128 Kb...

Страница 76: ...rganization on 1 Mbyte devices The dual bank feature on 1 Mbyte devices is enabled by setting the DB1M option bit To obtain a dual bank Flash memory the last 512 Kbytes of the single bank sectors 8 11...

Страница 77: ...803 FFFF 128 Kbytes Sector 6 0x0804 0000 0x0805 FFFF 128 Kbytes Sector 11 0x080E 0000 0x080F FFFF 128 Kbytes Bank 2 Sector 12 0x0810 0000 0x0810 3FFF 16 Kbytes Sector 13 0x0810 4000 0x0810 7FFF 16 Kby...

Страница 78: ...12 16 Kbytes Sector 9 128 Kbytes Sector 13 16 Kbytes Sector 10 128 Kbytes Sector 14 16 Kbytes Sector 11 128 Kbytes Sector 15 16 Kbytes Sector 16 64 Kbytes Sector 17 128 Kbytes Sector 18 128 Kbytes Sec...

Страница 79: ...or 2 0x0800 8000 0x0800 BFFF 16 Kbytes Sector 3 0x0800 C000 0x0800 FFFF 16 Kbyte Sector 4 0x0801 0000 0x0801 FFFF 64 Kbytes Sector 5 0x0802 0000 0x0803 FFFF 128 Kbytes Sector 6 0x0804 0000 0x0805 FFFF...

Страница 80: ...Hz by activating the over drive mode when VOS 1 0 0x11 the maximum value of fHCLK is 168 MHz It can be extended to 180 MHz by activating the over drive mode The over drive mode is not available when V...

Страница 81: ...eeded modify the CPU clock prescaler by writing the HPRE bits in RCC_CFGR 3 Check that the new CPU clock source or and the new CPU clock prescaler value is are taken into account by reading the clock...

Страница 82: ...celerator implements an instruction prefetch queue and branch cache which increases program execution speed from the 128 bit Flash memory Based on CoreMark benchmark the performance achieved thanks to...

Страница 83: ...his case miss the penalty in terms of number of cycles is at least equal to the number of wait states 2EAD INS IVES INS 2EAD INS IVES INS INS FETCH INS FETCH INS FETCH INS FETCH INS FETCH INS FETCH IN...

Страница 84: ...y setting the data cache enable DCEN bit in the FLASH_ACR register This feature works like the instruction cache memory but the retained data size is limited to 8 rows of 128 bits Note Data in user co...

Страница 85: ...t read operation indicates that the logical value was effectively written to the memory this value may not be retained To use VPP an external high voltage supply between 8 and 9 V must be applied to t...

Страница 86: ...x and SER bits are both set in the FLASH_CR register mass erase is performed If both MERx and SER bits are reset and the STRT bit is set an unpredictable behavior may occur without generating any erro...

Страница 87: ...ode execution If this cannot be done safely it is recommended to flush the caches by setting the DCRST and ICRST bits in the FLASH_CR register Note The I D cache should be flushed only when it is disa...

Страница 88: ...Program error flags WRPERR Protection error flag RDERR Read protection error flag for STM32F42xxx and STM32F43xxx devices only In this case if the error interrupt enable bit ERRIE is set in the FLASH_...

Страница 89: ...hen entering the Stop mode Reset event when entering the Standby mode Bit 7 nRST_STDBY 0 Reset generated when entering the Standby mode 1 No reset generated Bit 6 nRST_STOP 0 Reset generated when ente...

Страница 90: ...bug and boot from RAM features disabled Others Level 1 read protection of memories debug features limited USER User option byte This byte is used to configure the following features Select the watchdo...

Страница 91: ...B1M Dual bank 1 Mbyte Flash memory devices 0 1 Mbyte single Flash memory contiguous addresses in bank 1 1 1 Mbyte dual bank Flash memory The Flash memory is organized as two banks of 512 Kbytes each s...

Страница 92: ...omatically modified by first erasing the user configuration sector and then programming all the option bytes with the values contained in the FLASH_OPTCR register Modifying user option bytes on STM32F...

Страница 93: ...Flash memory and backup SRAM from user code are allowed When Level 1 is active programming the protection option byte RDP to Level 0 causes the Flash memory and the backup SRAM to be mass erased As a...

Страница 94: ...rite Erase Read Write Erase Main Flash Memory and Backup SRAM Level 1 NO NO 1 YES Level 2 NO YES Option Bytes Level 1 YES YES Level 2 NO NO OTP Level 1 NO NA YES NA Level 2 NO NA YES NA 1 The main Fla...

Страница 95: ...R or MER MER1 and SER 1 A sector erase is requested and the Sector Number SNB field is not valid A mass erase is requested while at least one of the user sector is write protected by option bit MER or...

Страница 96: ...WRPERR flag is set The modification of the users option bytes BOR_LEV RST_STDBY is allowed since none of the active nWRPi bits is reset and SPRMOD is kept active Note The active value of nWRPi bits i...

Страница 97: ...lock blocks 0 to 15 Each OTP data block can be programmed until the value 0x00 is programmed in the corresponding OTP lock byte The lock bytes must only contain 0x00 and 0xFF values otherwise the OTP...

Страница 98: ...DCRST Data cache reset 0 Data cache is not reset 1 Data cache is reset This bit can be written only when the D cache is disabled Bit 11 ICRST Instruction cache reset 0 Instruction cache is not reset...

Страница 99: ...ed Bit 12 DCRST Data cache reset 0 Data cache is not reset 1 Data cache is reset This bit can be written only when the D cache is disabled Bit 11 ICRST Instruction cache reset 0 Instruction cache is n...

Страница 100: ...ess 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 KEY 31 16 w w w w w w w w w w w w w w w w 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 KEY 15 0 w w w w w w w w w w w w w w w w Bits 31 0 FKEYR 31 0 FPEC k...

Страница 101: ...operation finishes or an error occurs 0 no Flash memory operation ongoing 1 Flash memory operation ongoing Bits 15 8 Reserved must be kept cleared Bit 7 PGSERR Programming sequence error Set by hardw...

Страница 102: ...leared by writing a 1 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved BSY r 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved RDERR PGSERR PGPERR PGAERR WRPERR Reserved OPERR EOP rc_w1 rc_w1 rc_...

Страница 103: ...Flash memory row Cleared by writing 1 Bit 4 WRPERR Write protection error Set by hardware when an address to be erased programmed belongs to a write protected part of the Flash memory Cleared by writ...

Страница 104: ...his bit enables the interrupt generation when the EOP bit in the FLASH_SR register goes to 1 0 Interrupt generation disabled 1 Interrupt generation enabled Bits 23 17 Reserved must be kept cleared Bit...

Страница 105: ...nsuccessful unlock operation this bit remains set until the next reset Bits 30 26 Reserved must be kept cleared Bit 25 ERRIE Error interrupt enable This bit enables the interrupt generation when the O...

Страница 106: ...e sector to erase 0000 sector 0 0001 sector 1 01011 sector 11 01100 not allowed 01101 not allowed 01110 not allowed 01111 not allowed 10000 section 12 10001 section 13 11011 sector 23 11100 not allowe...

Страница 107: ...hardware to software or from software to hardware a system reset is required to make the change effective Bit 4 Reserved must be kept cleared Always read as 0 Bits 3 2 BOR_LEV 1 0 BOR reset Level The...

Страница 108: ...1 Mbyte Flash memory single bank vs dual bank organization STM32F42xxx and STM32F43xxx and Table 9 1 Mbyte dual bank Flash memory organization STM32F42xxx and STM32F43xxx To perform an erase operation...

Страница 109: ...OR_LEV BOR reset Level These bits contain the supply level threshold that activates releases the reset They can be written to program a new BOR level By default BOR is off When the supply voltage VDD...

Страница 110: ...access 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved nWRP 11 0 rw rw rw rw rw rw rw rw rw rw rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved Bits 31 28 Reserved must be kept cleared Bi...

Страница 111: ...0x10 FLASH_CR LOCK Reserved EOPIE Reserved STRT Reserved PSIZ E 1 0 Reserved SNB 3 0 MER SER PG Reset value 1 0 0 0 0 0 0 0 0 0 0 0x14 FLASH_ OPTCR Reserved nWRP 11 0 RDP 7 0 nRST_STDBY nRST_STOP WDG...

Страница 112: ...Reserved nWRP 11 0 RDP 7 0 nRST_STDBY nRST_STOP WDG_SW BFB2 BOR_LEV 1 0 OPTSTRT OPTLOCK Reset value 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 0 1 0 1 0 1 0 1 1 1 0 1 1 0 1 0x18 FLASH_ OPTCR1 Reserved nWRP 11 0 Re...

Страница 113: ...of verifying the Flash memory integrity The CRC calculation unit helps compute a signature of the software during runtime to be compared with a reference signature generated at link time and stored at...

Страница 114: ...the RESET control bit in the CRC_CR register This operation does not affect the contents of the CRC_IDR register 4 4 CRC registers The CRC calculation unit contains two data registers and a control r...

Страница 115: ...erated by the RESET bit in the CRC_CR register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved RESET w Bits 31 1 Reserved must be kept at reset...

Страница 116: ...hen the main VDD supply is powered off Note Depending on the operating power supply range some peripheral may be used with limited functionality and performance For more details refer to section Gener...

Страница 117: ...m noise on the PCB The ADC voltage supply input is available on a separate VDDA pin An isolated supply ground connection is provided on pin VSSA To ensure a better accuracy of low voltage inputs the u...

Страница 118: ...tasheet for the value of tRSTTEMPO and VDD VBAT 0 6 V a current may be injected into VBAT through an internal diode connected between VDD and the power switch VBAT If the power supply battery connecte...

Страница 119: ...x respectively 2 Set the DBP bit in the PWR power control register PWR_CR for STM32F405xx 07xx and STM32F415xx 17xx and PWR power control register PWR_CR for STM32F42xxx and STM32F43xxx to enable acce...

Страница 120: ...e connected to one or two dedicated pins VCAP_1 and VCAP_2 available in all packages Specific pins must be connected either to VSS or VDD to activate or deactivate the voltage regulator These pins dep...

Страница 121: ...ins VCAP_1 and VCAP_2 available in all packages Specific pins must be connected either to VSS or VDD to activate or deactivate the voltage regulator These pins depend on the package When activated by...

Страница 122: ...hen the main regulator MR or the low power regulator LPR is enabled Low voltage mode Under drive mode the 1 2 V domain is preserved in reduced leakage mode This mode is only available when the main re...

Страница 123: ...SB_48MHz clock Note The PLLI2S and PLLSAI can be configured at the same time as the system PLL During the Over drive switch activation no peripheral clocks should be enabled The peripheral clocks must...

Страница 124: ...mains set and the Over drive mode is still enabled but not active ODSW bit is reset If the ODEN bit is reset instead the Over drive mode is disabled and the voltage regulator is switched back to the i...

Страница 125: ...ection in the device datasheet When the supply voltage VDD drops below the selected VBOR threshold a device reset is generated The BOR can be disabled by programming the device option bytes In this ca...

Страница 126: ...PVD thresholds 5 3 Low power modes By default the microcontroller is in Run mode after a system or a power on reset In Run mode the CPU is clocked by HCLK and the program code is executed Several low...

Страница 127: ...ding bit in the NVIC interrupt clear pending register have to be cleared Only NVIC interrupts with sufficient priority will wakeup and interrupt the MCU When SEVONPEND 1 in the Cortex M4 with FPU Syst...

Страница 128: ...ons Table 23 Low power mode summary Mode name Entry Wakeup Effect on 1 2 V domain clocks Effect on VDD domain clocks Voltage regulator Sleep Sleep now or Sleep on exit WFI or Return from ISR Any inter...

Страница 129: ...de can be performed automatically by resetting the corresponding bit in RCC_AHBxLPENR and RCC_APBxLPENR registers 5 3 3 Sleep mode Entering Sleep mode The Sleep mode is entered according to Section En...

Страница 130: ...61 Vector table for STM32F405xx 07xx and STM32F415xx 17xx and Table 62 Vector table for STM32F42xxx and STM32F43xxx If WFE was used for entry and SEVONPEND 0 Wakeup event Refer to Section 12 2 3 Wakeu...

Страница 131: ...iting to its Key register or by hardware option Once started it cannot be stopped except by a Reset See Section 21 3 in Section 21 Independent watchdog IWDG Real time clock RTC this is configured by t...

Страница 132: ...n additional startup delay is incurred when waking up from Stop mode By keeping the internal regulator ON during Stop mode the consumption is higher although the startup time is reduced Table 27 Stop...

Страница 133: ...The interrupt source can be external interrupts or peripherals with wakeup capability Refer to Table 61 Vector table for STM32F405xx 07xx and STM32F415xx 17xx on page 374 and Table 62 Vector table fo...

Страница 134: ...main is ongoing The Stop mode entry is delayed until the APB access is finished If the Over drive mode was enabled before entering Stop mode it is automatically disabled during when the Stop mode is a...

Страница 135: ...e them the ADON bit in the ADC_CR2 register and the ENx bit in the DAC_CR register must both be written to 0 Note Before entering Stop mode it is recommended to enable the clock security system CSS fe...

Страница 136: ...CR1 Note To enter Stop mode all EXTI Line pending bits in Pending register EXTI_PR all peripheral interrupts pending bits the RTC Alarm Alarm A and Alarm B RTC wakeup RTC tamper and RTC time stamp fla...

Страница 137: ...2 PWR power control status register PWR_CSR for STM32F405xx 07xx and STM32F415xx 17xx indicates that the MCU was in Standby mode All registers are reset after wakeup from Standby except for PWR_CR Re...

Страница 138: ...C alternate function The RTC alternate functions are the RTC alarms Alarm A and Alarm B RTC wakeup RTC tamper event detection and RTC time stamp event detection These RTC alternate functions can wake...

Страница 139: ...mode To wake up the device from the Standby mode with an RTC alarm event it is necessary to a Enable the RTC alarm interrupt in the RTC_CR register b Configure the RTC to generate the RTC alarm To wa...

Страница 140: ...interrupt e Re enter the low power mode When using RTC tamper to wake up the device from the low power modes a Disable the RTC tamper interrupt TAMPIE bit in the RTC_TAFCR register b Clear the Tamper...

Страница 141: ...set value Bit 9 FPDS Flash power down in Stop mode When set the Flash memory enters power down mode when the device enters Stop mode This allows to achieve a lower consumption in stop mode but a longe...

Страница 142: ...the WUF Wakeup Flag after 2 System clock cycles Bit 1 PDDS Power down deepsleep This bit is set and cleared by software It works together with the LPDS bit 0 Enter Stop mode when the CPU enters deepsl...

Страница 143: ...be kept at reset value Bit 3 BRR Backup regulator ready Set by hardware to indicate that the Backup Regulator is ready 0 Backup Regulator not ready 1 Backup Regulator ready Note This bit is not reset...

Страница 144: ...10 Reserved 11 Under drive enable Bit 17 ODSWEN Over drive switching enabled This bit is set by software It is cleared automatically by hardware after exiting from Stop mode or when the ODEN bit is re...

Страница 145: ...when the device is in Stop mode 1 Main Regulator in under drive mode and Flash memory in power down when the device is in Stop under drive mode Bit 10 LPUDS Low power regulator in deepsleep under driv...

Страница 146: ...F Clear standby flag This bit is always read as 0 0 No effect 1 Clear the SBF Standby Flag write Bit 2 CWUF Clear wakeup flag This bit is always read as 0 0 No effect 1 Clear the WUF Wakeup Flag after...

Страница 147: ...ed in Stop mode Bit 17 ODSWRDY Over drive mode switching ready 0 Over drive mode is not active 1 Over drive mode is active on digital area on 1 2 V domain Bit 16 ODRDY Over drive mode ready 0 Over dri...

Страница 148: ...nabled by the PVDE bit 0 VDD is higher than the PVD threshold selected with the PLS 2 0 bits 1 VDD is lower than the PVD threshold selected with the PLS 2 0 bits Note The PVD is stopped by Standby mod...

Страница 149: ...BF CWUF PDDS LPDS Reset value 1 0 0 0 0 0 0 0 0 0 0 0x004 PWR_CSR Reserved VOSRDY Reserved BRE EWUP Reserved BRR PVDO SBF WUF Reset value 0 0 0 0 0 0 0 Table 32 PWR register map and reset values for S...

Страница 150: ...The SYSRESETREQ bit in Cortex M4 with FPU Application Interrupt and Reset Control Register must be set to force a software reset on the device Refer to the Cortex M4 with FPU technical reference manua...

Страница 151: ...e BKPSRAM is not affected by this reset The only way of resetting the BKPSRAM is through the Flash interface by requesting a protection level change from 1 to 0 A backup domain reset is generated when...

Страница 152: ...WKHUQHW 0 6 7 B0 B7 B B0 27 B 6B6 3 6 RUWH IUHH UXQQLQJ FORFN 3 SHULSKHUDO FORFNV 0 FORFNV 86 6 8 3 FORFN WKHUQHW 373 FORFN 0 2 0 2 7 B0 B5 B B0 26 B 1 26 B287 7R QGHSHQGHQW ZDWFKGRJ 6 6 WR 57 57 57 6...

Страница 153: ...AI1 peripheral in case the PLLI2S is programmed to achieve another audio sampling frequency 49 152 MHz or 11 2896 MHz and the application requires both frequencies at the same time LTDC clock The LTDC...

Страница 154: ...ode by setting the HSEBYP and HSEON bits in the RCC clock control register RCC_CR The external clock signal square sinus or triangle with 50 duty cycle has to drive the OSC_IN pin while the OSC_OUT pi...

Страница 155: ...stable or not At startup the HSI RC output clock is not released until this bit is set by hardware The HSI RC can be switched on and off using the HSION bit in the RCC clock control register RCC_CR Th...

Страница 156: ...ON bits in the RCC Backup domain control register RCC_BDCR The external clock signal square sinus or triangle with 50 duty cycle has to drive the OSC32_IN pin while the OSC32_OUT pin should be left HI...

Страница 157: ...e system clock when the failure occurred PLL is also disabled In this case if the PLLI2S was enabled it is also disabled when the HSE fails 6 2 8 RTC AWU clock Once the RTCCLK clock source has been se...

Страница 158: ...he desired clock source is selected using the MCO1PRE 2 0 and MCO1 1 0 bits in the RCC clock configuration register RCC_CFGR MCO2 You can output four different clock sources onto the MCO2 pin PC9 usin...

Страница 159: ...the precision of the HSI The measured value can be used to have more accurate RTC time base timeouts when LSI is used as the RTC clock source and or an IWDG timeout with an acceptable accuracy Use the...

Страница 160: ...Reset and clock control for STM32F42xxx and STM32F43xxx RCC RM0090 160 1731 DocID018909 Rev 11 Figure 19 Frequency measurement with TIM11 in Input capture mode 4 4 4 2 0 0 3 24 Z AI...

Страница 161: ...t reset value Bit 29 PLLSAIRDY PLLSAI clock ready flag Set by hardware to indicate that the PLLSAI is locked 0 PLLSAI unlocked 1 PLLSAI locked Bit 28 PLLSAION PLLSAI enable Set and cleared by software...

Страница 162: ...clock enable Set and cleared by software Cleared by hardware to stop the HSE oscillator when entering Stop or Standby mode This bit cannot be reset if the HSE oscillator is used directly or indirectl...

Страница 163: ...n PLL PLL division factor for USB OTG FS SDIO and random number generator clocks Set and cleared by software to control the frequency of USB OTG FS clock the random number generator clock and the SDIO...

Страница 164: ...ut frequency PLLN with 50 PLLN 432 000000000 PLLN 0 wrong configuration 000000001 PLLN 1 wrong configuration 000110010 PLLN 50 001100011 PLLN 99 001100100 PLLN 100 110110000 PLLN 432 110110001 PLLN 43...

Страница 165: ...ck selected 11 PLL clock selected Bits 27 29 MCO2PRE MCO2 prescaler Set and cleared by software to configure the prescaler of the MCO2 Modification of this prescaler may generate glitches on MCO2 It i...

Страница 166: ...no clock 00010 HSE 2 00011 HSE 3 00100 HSE 4 11110 HSE 30 11111 HSE 31 Bits 15 13 PPRE2 APB high speed prescaler APB2 Set and cleared by software to control APB high speed clock division factor Cautio...

Страница 167: ...ock switch status Set and cleared by hardware to indicate which clock source is used as the system clock 00 HSI oscillator used as the system clock 01 HSE oscillator used as the system clock 10 PLL us...

Страница 168: ...Bit 19 HSERDYC HSE ready interrupt clear This bit is set by software to clear the HSERDYF flag 0 No effect 1 HSERDYF cleared Bit 18 HSIRDYC HSI ready interrupt clear This bit is set software to clear...

Страница 169: ...e to enable disable interrupt caused by LSI oscillator stabilization 0 LSI ready interrupt disabled 1 LSI ready interrupt enabled Bit 7 CSSF Clock security system interrupt flag This bit is set by har...

Страница 170: ...External Low Speed clock becomes stable and LSERDYDIE is set It is cleared by software by setting the LSERDYC bit 0 No clock ready interrupt caused by the LSE oscillator 1 Clock ready interrupt caused...

Страница 171: ...2 Bits 20 13 Reserved must be kept at reset value Bit 12 CRCRST CRC reset This bit is set and cleared by software 0 does not reset CRC 1 resets CRC Bit 11 Reserved must be kept at reset value Bit 10 G...

Страница 172: ...t IO port E 1 resets IO port E Bit 3 GPIODRST IO port D reset This bit is set and cleared by software 0 does not reset IO port D 1 resets IO port D Bit 2 GPIOCRST IO port C reset This bit is set and c...

Страница 173: ...and cleared by software 0 does not reset the USB OTG FS module 1 resets the USB OTG FS module Bit 6 RNGRST Random number generator module reset Set and cleared by software 0 does not reset the random...

Страница 174: ...1 10 9 8 7 6 5 4 3 2 1 0 Reserved FMCRST rw Bits 31 1 Reserved must be kept at reset value Bit 0 FMCRST Flexible memory controller module reset Set and cleared by software 0 does not reset the FMC mod...

Страница 175: ...e Bit 27 Reserved must be kept at reset value Bit 26 CAN2RST CAN2 reset Set and cleared by software 0 does not reset CAN2 1 resets CAN2 Bit 25 CAN1RST CAN1 reset Set and cleared by software 0 does not...

Страница 176: ...2 1 resets SPI2 Bits 13 12 Reserved must be kept at reset value Bit 11 WWDGRST Window watchdog reset Set and cleared by software 0 does not reset the window watchdog 1 resets the window watchdog Bits...

Страница 177: ...and cleared by software 0 does not reset TIM5 1 resets TIM5 Bit 2 TIM4RST TIM4 reset Set and cleared by software 0 does not reset TIM4 1 resets TIM4 Bit 1 TIM3RST TIM3 reset Set and cleared by softwa...

Страница 178: ...reset value Bit 26 LTDCRST LTDC reset This bit is set and reset by software 0 does not reset LCD TFT 1 resets LCD TFT Bits 27 23 Reserved must be kept at reset value Bit 22 SAI1RST SAI1 reset This bit...

Страница 179: ...eared by software 0 does not reset the SDIO module 1 resets the SDIO module Bits 10 9 Reserved must be kept at reset value Bit 8 ADCRST ADC interface reset common to all ADCs This bit is set and clear...

Страница 180: ...software 0 USB OTG HS ULPI clock disabled 1 USB OTG HS ULPI clock enabled Bit 29 OTGHSEN USB OTG HS clock enable This bit is set and cleared by software 0 USB OTG HS clock disabled 1 USB OTG HS clock...

Страница 181: ...ce clock enabled Bits 17 13 Reserved must be kept at reset value Bit 12 CRCEN CRC clock enable This bit is set and cleared by software 0 CRC clock disabled 1 CRC clock enabled Bit 11 Reserved must be...

Страница 182: ...ble This bit is set and cleared by software 0 IO port C clock disabled 1 IO port C clock enabled Bit 1 GPIOBEN IO port B clock enable This bit is set and cleared by software 0 IO port B clock disabled...

Страница 183: ...3 1 Reserved must be kept at reset value Bit 0 DCMIEN Camera interface enable This bit is set and cleared by software 0 Camera interface clock disabled 1 Camera interface clock enabled 31 30 29 28 27...

Страница 184: ...Bit 26 CAN2EN CAN 2 clock enable This bit is set and cleared by software 0 CAN 2 clock disabled 1 CAN 2 clock enabled Bit 25 CAN1EN CAN 1 clock enable This bit is set and cleared by software 0 CAN 1 c...

Страница 185: ...ts 13 12 Reserved must be kept at reset value Bit 11 WWDGEN Window watchdog clock enable This bit is set and cleared by software 0 Window watchdog clock disabled 1 Window watchdog clock enabled Bit 10...

Страница 186: ...ock disabled 1 TIM5 clock enabled Bit 2 TIM4EN TIM4 clock enable This bit is set and cleared by software 0 TIM4 clock disabled 1 TIM4 clock enabled Bit 1 TIM3EN TIM3 clock enable This bit is set and c...

Страница 187: ...le This bit is set and cleared by software 0 LTDC clock disabled 1 LTDC clock enabled Bits 27 23 Reserved must be kept at reset value Bit 22 SAI1EN SAI1 clock enable This bit is set and cleared by sof...

Страница 188: ...le This bit is set and cleared by software 0 ADC3 clock disabled 1 ADC3 clock disabled Bit 9 ADC2EN ADC2 clock enable This bit is set and cleared by software 0 ADC2 clock disabled 1 ADC2 clock disable...

Страница 189: ...N USB OTG HS clock enable during Sleep mode This bit is set and cleared by software 0 USB OTG HS clock disabled during Sleep mode 1 USB OTG HS clock enabled during Sleep mode Bit 28 ETHMACPTPLPEN Ethe...

Страница 190: ...bit is set and cleared by software 0 SRAM2 interface clock disabled during Sleep mode 1 SRAM2 interface clock enabled during Sleep mode Bit 16 SRAM1LPEN SRAM1 interface clock enable during Sleep mode...

Страница 191: ...during Sleep mode 1 IO port F clock enabled during Sleep mode Bit 4 GPIOELPEN IO port E clock enable during Sleep mode Set and cleared by software 0 IO port E clock disabled during Sleep mode 1 IO po...

Страница 192: ...Bit 6 RNGLPEN Random number generator clock enable during Sleep mode This bit is set and cleared by software 0 Random number generator clock disabled during Sleep mode 1 Random number generator clock...

Страница 193: ...Reserved FMC LPEN rw Bits 31 1Reserved must be kept at reset value Bit 0 FMCLPEN Flexible memory controller module clock enable during Sleep mode This bit is set and cleared by software 0 FMC module...

Страница 194: ...software 0 CAN 2 clock disabled during sleep mode 1 CAN 2 clock enabled during sleep mode Bit 25 CAN1LPEN CAN 1 clock enable during Sleep mode This bit is set and cleared by software 0 CAN 1 clock di...

Страница 195: ...LPEN Window watchdog clock enable during Sleep mode This bit is set and cleared by software 0 Window watchdog clock disabled during sleep mode 1 Window watchdog clock enabled during sleep mode Bits 10...

Страница 196: ...ock enable during Sleep mode This bit is set and cleared by software 0 TIM4 clock disabled during Sleep mode 1 TIM4 clock enabled during Sleep mode Bit 1 TIM3LPEN TIM3 clock enable during Sleep mode T...

Страница 197: ...isabled during Sleep mode 1 LTDC clock enabled during Sleep mode Bits 25 23 Reserved must be kept at reset value Bit 22 SAI1LPEN SAI1 clock enable during Sleep mode This bit is set and cleared by soft...

Страница 198: ...Bit 11 SDIOLPEN SDIO clock enable during Sleep mode This bit is set and cleared by software 0 SDIO module clock disabled during Sleep mode 1 SDIO module clock enabled during Sleep mode Bit 10 ADC3LPE...

Страница 199: ...3 2 Reserved must be kept at reset value Bit 1 TIM8LPEN TIM8 clock enable during Sleep mode This bit is set and cleared by software 0 TIM8 clock disabled during Sleep mode 1 TIM8 clock enabled during...

Страница 200: ...selection through the RTCPRE 4 0 bits in the RCC clock configuration register RCC_CFGR used as the RTC clock Bits 7 3 Reserved must be kept at reset value Bit 2 LSEBYP External low speed oscillator by...

Страница 201: ...by writing to the RMVF bit 0 No watchdog reset occurred 1 Watchdog reset occurred Bit 28 SFTRSTF Software reset flag This bit is set by hardware when a software reset occurs Cleared by writing to the...

Страница 202: ...o indicate when the internal RC 40 kHz oscillator is stable After the LSION bit is cleared LSIRDY goes low after 3 LSI clock cycles 0 LSI RC oscillator not ready 1 LSI RC oscillator ready Bit 0 LSION...

Страница 203: ...at reset value Bits 27 13 INCSTEP Incrementation step These bits are set and cleared by software To write before setting CR 24 PLLON bit Configuration input for modulation profile amplitude Bits 12 0...

Страница 204: ...tion about I2S clock frequency and precision refer to Section 28 4 4 Clock generator in the I2S chapter Caution The I2Ss requires a frequency lower than or equal to 192 MHz to work correctly I2S clock...

Страница 205: ...e that the VCO output frequency is between 100 and 432 MHz VCO output frequency VCO input frequency PLLI2SN with 50 PLLI2SN 432 000000000 PLLI2SN 0 wrong configuration 000000001 PLLI2SN 1 wrong config...

Страница 206: ...rved PLLSAIN Reserved rw rw rw rw rw rw rw rw rw Bit 31 Reserved must be kept at reset value Bits 30 28 PLLSAIR PLLSAI division factor for LCD clock Set and reset by software to control the LCD clock...

Страница 207: ...alf word and word accesses are allowed to write these bits Caution The software has to set these bits correctly to ensure that the VCO output frequency is between 100 and 432 MHz VCO output frequency...

Страница 208: ...ts are set and cleared by software to control the SAI1 B clock frequency They should be written when the PLLSAI and PLLI2S are disabled 00 SAI1 B clock frequency f PLLSAI_Q PLLSAIDIVQ 01 SAI1 B clock...

Страница 209: ...LSAIDIVQ 31 00000 PLLSAIDIVQ 1 00001 PLLSAIDIVQ 2 00010 PLLSAIDIVQ 3 00011 PLLSAIDIVQ 4 00100 PLLSAIDIVQ 5 11111 PLLSAIDIVQ 32 Bits 7 5 Reserved must be kept at reset value Bits 4 0 PLLI2SDIVQ PLLI2S...

Страница 210: ...DYIE PLLRDYIE HSERDYIE HSIRDYIE LSERDYIE LSIRDYIE CSSF PLLSAIRDYF PLLI2SRDYF PLLRDYF HSERDYF HSIRDYF LSERDYF LSIRDYF 0x10 RCC_AHB1RS TR Reserved OTGHSRST Reserved ETHMACRST Reserved DMA2DRST DMA2RST D...

Страница 211: ...PEN 0x58 RCC_AHB3LP ENR Reserved FMCLPEN 0x5C Reserved Reserved 0x60 RCC_APB1LP ENR UART8LPEN UART7LPEN DACLPEN PWRLPEN Reserved CAN2LPEN CAN1LPEN Reserved I2C3LPEN I2C2LPEN I2C1LPEN UART5LPEN UART4LP...

Страница 212: ...resses 0x88 RCC_PLLSAI CFGR PLLSAIR PLLSAIQ Reserved PLLSAIN Reserved 0x8C RCC_DCKCF GR Reserved TIMPRE SAI1BSCR SAI1ASCR Reserved PLLSAIDIVR Reserved PLLSAIDIVQ Reserved PLLI2SDIVQ Table 33 RCC regis...

Страница 213: ...ystem reset is generated when one of the following events occurs 1 A low level on the NRST pin external reset 2 Window watchdog end of count condition WWDG reset 3 Independent watchdog end of count co...

Страница 214: ...ode A power reset sets all registers to their reset values except the Backup domain see Figure 4 These sources act on the NRST pin and it is always kept low during the delay phase The RESET service ro...

Страница 215: ...ff 7 2 Clocks Three different clock sources can be used to drive the system clock SYSCLK HSI oscillator clock HSE oscillator clock Main PLL PLL clock The devices have the two following secondary clock...

Страница 216: ...FORFN 3 SHULSKHUDO FORFNV 3 WLPHU FORFNV 0 FORFNV 86 6 8 3 FORFN WKHUQHW 373 FORFN 0 2 3HULSKHUDO FORFN HQDEOH WR 0 2 DL G 7 B0 B5 B B0 26 B 1 26 B287 6 26 N 6 5 N WR LQGHSHQGHQW ZDWFKGRJ 6 6 WR 57 57...

Страница 217: ...clock which is provided from the external PHY The Ethernet MAC clocks TX RX and RMII which are provided from the external PHY For further information on the Ethernet configuration please refer to Sec...

Страница 218: ...l register RCC_CR indicates if the high speed external oscillator is stable or not At startup the clock is not released until this bit is set by hardware An interrupt can be generated if enabled in th...

Страница 219: ...the high speed system clock up to 168 MHz The second output is used to generate the clock for the USB OTG FS 48 MHz the random analog generator 48 MHz and the SDIO 48 MHz A dedicated PLL PLLI2S used t...

Страница 220: ...he RCC clock interrupt register RCC_CIR 7 2 6 System clock SYSCLK selection After a system reset the HSI oscillator is selected as the system clock When a clock source is used directly or through PLL...

Страница 221: ...e AWU clock the AWU state is not guaranteed if the system supply disappears If the HSE oscillator divided by a value between 2 and 31 is used as the RTC clock the RTC state is not guaranteed if the ba...

Страница 222: ...ternal clock measurement using TIM5 TIM11 It is possible to indirectly measure the frequencies of all on board clock source generators by means of the input capture of TIM5 channel4 and TIM11 channel1...

Страница 223: ...to 0x01 to connect the LSI clock internally to TIM5 channel4 input capture for calibration purposes 3 Measure the LSI clock frequency using the TIM5 capture compare 4 event or interrupt 4 Use the meas...

Страница 224: ...the PLLI2S is locked 0 PLLI2S unlocked 1 PLLI2S locked Bit 26 PLLI2SON PLLI2S enable Set and cleared by software to enable PLLI2S Cleared by hardware when entering Stop or Standby mode 0 PLLI2S OFF 1...

Страница 225: ...em clock 0 HSE oscillator OFF 1 HSE oscillator ON Bits 15 8 HSICAL 7 0 Internal high speed clock calibration These bits are initialized automatically at startup Bits 7 3 HSITRIM 4 0 Internal high spee...

Страница 226: ...Main PLL PLL division factor for USB OTG FS SDIO and random number generator clocks Set and cleared by software to control the frequency of USB OTG FS clock the random number generator clock and the S...

Страница 227: ...VCO input frequency PLLN with 50 PLLN 432 000000000 PLLN 0 wrong configuration 000000001 PLLN 1 wrong configuration 000110010 PLLN 50 001100011 PLLN 99 001100100 PLLN 100 110110000 PLLN 432 110110001...

Страница 228: ...clock selected 11 PLL clock selected Bits 27 29 MCO2PRE MCO2 prescaler Set and cleared by software to configure the prescaler of the MCO2 Modification of this prescaler may generate glitches on MCO2 I...

Страница 229: ...00001 no clock 00010 HSE 2 00011 HSE 3 00100 HSE 4 11110 HSE 30 11111 HSE 31 Bits 15 13 PPRE2 APB high speed prescaler APB2 Set and cleared by software to control APB high speed clock division factor...

Страница 230: ...2 SWS System clock switch status Set and cleared by hardware to indicate which clock source is used as the system clock 00 HSI oscillator used as the system clock 01 HSE oscillator used as the system...

Страница 231: ...lear This bit is set software to clear the HSIRDYF flag 0 No effect 1 HSIRDYF cleared Bit 17 LSERDYC LSE ready interrupt clear This bit is set by software to clear the LSERDYF flag 0 No effect 1 LSERD...

Страница 232: ...s detected in the HSE oscillator Cleared by software setting the CSSC bit 0 No clock security interrupt caused by HSE clock failure 1 Clock security interrupt caused by HSE clock failure Bits 6 Reserv...

Страница 233: ...scillator Bit 0 LSIRDYF LSI ready interrupt flag Set by hardware when the internal low speed clock becomes stable and LSIRDYDIE is set Cleared by software setting the LSIRDYC bit 0 No clock ready inte...

Страница 234: ...pt at reset value Bit 8 GPIOIRST IO port I reset Set and cleared by software 0 does not reset IO port I 1 resets IO port I Bit 7 GPIOHRST IO port H reset Set and cleared by software 0 does not reset I...

Страница 235: ...2 GPIOCRST IO port C reset Set and cleared by software 0 does not reset IO port C 1 resets IO port C Bit 1 GPIOBRST IO port B reset Set and cleared by software 0 does not reset IO port B 1 resets IO...

Страница 236: ...Set and cleared by software 0 does not reset the USB OTG FS module 1 resets the USB OTG FS module Bit 6 RNGRST Random number generator module reset Set and cleared by software 0 does not reset the ran...

Страница 237: ...nd cleared by software 0 does not reset the FSMC module 1 resets the FSMC module 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved DACRST PWR RST Reser ved CAN2 RST CAN1 RST Reser ved I2C3 RST...

Страница 238: ...I2C2 Bit 21 I2C1RST I2C1 reset Set and cleared by software 0 does not reset I2C1 1 resets I2C1 Bit 20 UART5RST UART5 reset Set and cleared by software 0 does not reset UART5 1 resets UART5 Bit 19 UART...

Страница 239: ...software 0 does not reset TIM13 1 resets TIM13 Bit 6 TIM12RST TIM12 reset Set and cleared by software 0 does not reset TIM12 1 resets TIM12 Bit 5 TIM7RST TIM7 reset Set and cleared by software 0 does...

Страница 240: ...18 TIM11RST TIM11 reset Set and cleared by software 0 does not reset TIM11 1 resets TIM14 Bit 17 TIM10RST TIM10 reset Set and cleared by software 0 does not reset TIM10 1 resets TIM10 Bit 16 TIM9RST T...

Страница 241: ...6 Reserved must be kept at reset value Bit 5 USART6RST USART6 reset Set and cleared by software 0 does not reset USART6 1 resets USART6 Bit 4 USART1RST USART1 reset Set and cleared by software 0 does...

Страница 242: ...enable Set and cleared by software 0 USB OTG HS ULPI clock disabled 1 USB OTG HS ULPI clock enabled Bit 29 OTGHSEN USB OTG HS clock enable Set and cleared by software 0 USB OTG HS clock disabled 1 USB...

Страница 243: ...Set and cleared by software 0 CRC clock disabled 1 CRC clock enabled Bits 11 9 Reserved must be kept at reset value Bit 8 GPIOIEN IO port I clock enable Set and cleared by software 0 IO port I clock d...

Страница 244: ...t A clock enable Set and cleared by software 0 IO port A clock disabled 1 IO port A clock enabled 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserve...

Страница 245: ...mera interface enable Set and cleared by software 0 Camera interface clock disabled 1 Camera interface clock enabled 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6...

Страница 246: ...N1EN CAN 1 clock enable Set and cleared by software 0 CAN 1 clock disabled 1 CAN 1 clock enabled Bit 24 Reserved must be kept at reset value Bit 23 I2C3EN I2C3 clock enable Set and cleared by software...

Страница 247: ...et and cleared by software 0 Window watchdog clock disabled 1 Window watchdog clock enabled Bits 10 9 Reserved must be kept at reset value Bit 8 TIM14EN TIM14 clock enable Set and cleared by software...

Страница 248: ...clock disabled 1 TIM2 clock enabled 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved TIM11 EN TIM10 EN TIM9 EN rw rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reser ved SYSCF G EN Reser ved SPI...

Страница 249: ...et and cleared by software 0 ADC3 clock disabled 1 ADC3 clock disabled Bit 9 ADC2EN ADC2 clock enable Set and cleared by software 0 ADC2 clock disabled 1 ADC2 clock disabled Bit 8 ADC1EN ADC1 clock en...

Страница 250: ...cleared by software 0 SPI6 clock disabled 1 SPI6 clock enabled Bit 20 SPI5EN SPI5 clock enable Set and cleared by software 0 SPI5 clock disabled 1 SPI5 clock enabled Bit 19 Reserved must be kept at r...

Страница 251: ...ed by software 0 ADC2 clock disabled 1 ADC2 clock disabled Bit 8 ADC1EN ADC1 clock enable Set and cleared by software 0 ADC1 clock disabled 1 ADC1 clock disabled Bits 7 6 Reserved must be kept at rese...

Страница 252: ...Bit 29 OTGHSLPEN USB OTG HS clock enable during Sleep mode Set and cleared by software 0 USB OTG HS clock disabled during Sleep mode 1 USB OTG HS clock enabled during Sleep mode Bit 28 ETHMACPTPLPEN E...

Страница 253: ...TFLPEN Flash interface clock enable during Sleep mode Set and cleared by software 0 Flash interface clock disabled during Sleep mode 1 Flash interface clock enabled during Sleep mode Bits 14 13 Reserv...

Страница 254: ...d during Sleep mode Bit 1 GPIOBLPEN IO port B clock enable during Sleep mode Set and cleared by software 0 IO port B clock disabled during Sleep mode 1 IO port B clock enabled during Sleep mode Bit 0...

Страница 255: ...and cleared by software 0 cryptography modules clock disabled during Sleep mode 1 cryptography modules clock enabled during Sleep mode Bits 3 1 Reserved must be kept at reset value Bit 0 DCMILPEN Came...

Страница 256: ...t and cleared by software 0 DAC interface clock disabled during Sleep mode 1 DAC interface clock enabled during Sleep mode Bit 28 PWRLPEN Power interface clock enable during Sleep mode Set and cleared...

Страница 257: ...RT2 clock disabled during Sleep mode 1 USART2 clock enabled during Sleep mode Bit 16 Reserved must be kept at reset value Bit 15 SPI3LPEN SPI3 clock enable during Sleep mode Set and cleared by softwar...

Страница 258: ...IM6 clock disabled during Sleep mode 1 TIM6 clock enabled during Sleep mode Bit 3 TIM5LPEN TIM5 clock enable during Sleep mode Set and cleared by software 0 TIM5 clock disabled during Sleep mode 1 TIM...

Страница 259: ...ng Sleep mode Bit 17 TIM10LPEN TIM10 clock enable during Sleep mode Set and cleared by software 0 TIM10 clock disabled during Sleep mode 1 TIM10 clock enabled during Sleep mode Bit 16 TIM9LPEN TIM9 cl...

Страница 260: ...bled during Sleep mode Bits 7 6 Reserved must be kept at reset value Bit 5 USART6LPEN USART6 clock enable during Sleep mode Set and cleared by software 0 USART6 clock disabled during Sleep mode 1 USAR...

Страница 261: ...3 12 11 10 9 8 7 6 5 4 3 2 1 0 RTCEN Reserved RTCSEL 1 0 Reserved LSEBY P LSERD Y LSEON rw rw rw rw r rw Bits 31 17 Reserved must be kept at reset value Bit 16 BDRST Backup domain software reset Set a...

Страница 262: ...ready 1 LSE clock ready Bit 0 LSEON External low speed oscillator enable Set and cleared by software 0 LSE clock OFF 1 LSE clock ON 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 LPWR RSTF WWDG RSTF...

Страница 263: ...ST pin occurred 1 Reset from NRST pin occurred Bit 25 BORRSTF BOR reset flag Cleared by software by writing the RMVF bit Set by hardware when a POR PDR or BOR reset occurs 0 No POR PDR or BOR reset oc...

Страница 264: ...served INCSTEP rw rw rw rw rw rw rw rw rw rw rw rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 INCSTEP MODPER rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw Bit 31 SSCGEN Spread spectrum modulation enab...

Страница 265: ...5 PLLI2SN 4 PLLI2SN 3 PLLI2SN 2 PLLI2SN 1 PLLI2SN 0 Reserved rw rw rw rw rw rw rw rw rw Bit 31 Reserved must be kept at reset value Bits 30 28 PLLI2SR PLLI2S division factor for I2S clocks Set and cle...

Страница 266: ...sure that the VCO output frequency is between 100 and 432 MHz VCO output frequency VCO input frequency PLLI2SN with 50 PLLI2SN 432 000000000 PLLI2SN 0 wrong configuration 000000001 PLLI2SN 1 wrong con...

Страница 267: ...DYC LSIRDYC Reserved PLLI2SRDYIE PLLRDYIE HSERDYIE HSIRDYIE LSERDYIE LSIRDYIE CSSF Reserved PLLI2SRDYF PLLRDYF HSERDYF HSIRDYF LSERDYF LSIRDYF 0x10 RCC_ AHB1RSTR Reserved OTGHSRST Reserved ETHMACRST R...

Страница 268: ...PEN RNGLPEN HASHLPEN CRYPLPEN Reserved DCMILPEN 0x58 RCC_AHB3LP ENR Reserved FSMCLPEN 0x5C Reserved Reserved 0x60 RCC_APB1LP ENR Reserved DACLPEN PWRLPEN Reserved CAN2LPEN CAN1LPEN Reserved I2C3LPEN I...

Страница 269: ...nput data register GPIOx_IDR or peripheral alternate function input Bit set and reset register GPIOx_BSRR for bitwise write access to GPIOx_ODR Locking mechanism GPIOx_LCKR provided to freeze the I O...

Страница 270: ...bit 1 VDD_FT is a potential specific to five volt tolerant I Os and different from VDD Table 35 Port bit configuration table 1 MODER i 1 0 OTYPER i OSPEEDR i B A PUPDR i 1 0 I O configuration 01 0 SPE...

Страница 271: ...ly the N MOS is activated when 0 is output The input data register GPIOx_IDR captures the data present on the I O pin at every AHB1 clock cycle All GPIO pins have weak internal pull up and pull down r...

Страница 272: ...NTOUT is mapped on AF15 This structure is shown in Figure 26 below In addition to this flexible I O multiplexing architecture each peripheral has alternate functions mapped onto different I O pins to...

Страница 273: ...in the GPIOx_AFRL or GPIOx_AFRH register EVENTOUT Configure the I O pin used to output the Cortex M4 with FPU EVENTOUT signal by connecting it to AF15 Note EVENTOUT is not mapped onto the following I...

Страница 274: ...ed in FS DL RU SLQV WR WKH 3 2 B 5 UHJLVWHU VHOHFWV WKH GHGLFDWHG DOWHUQDWH IXQFWLRQ V VWHP 7 0 7 0 7 0 7 0 63 63 63 86 57 86 57 1 1 7 0 27 B 6 27 B 6 7 60 6 2 27 B 6 0 9 17287 3LQ 5 RU SLQV WR WKH 3...

Страница 275: ...d STM32F43xxx 1 Configured in FS 3 6 OR PINS TO THE 0 X 2 REGISTER SELECTS THE DEDICATED ALTERNATE FUNCTION SYSTEM 4 4 4 4 30 30 3 53 24 53 24 4 4 4 3 4 3 4 3 4 3 4 6 4 54 0IN X X 2 OR PINS TO THE 0 X...

Страница 276: ...GPIOx_ODR To each bit in GPIOx_ODR correspond two control bits in GPIOx_BSRR BSRR i and BSRR i SIZE When written to 1 bit BSRR i sets the corresponding ODR i bit When written to 1 bit BSRR i SIZE rese...

Страница 277: ...lternate function registers The application can thus select any one of the possible functions for each I O The AF selection signal being common to the alternate function input and alternate function o...

Страница 278: ...tes the P MOS The Schmitt trigger input is activated The weak pull up and pull down resistors are activated or not depending on the value in the GPIOx_PUPDR register The data present on the I O pin ar...

Страница 279: ...ead access to the input data register gets the I O state Figure 30 shows the Alternate function configuration of the I O port bit Figure 30 Alternate function configuration 0USH PULL OR PEN DRAIN UTPU...

Страница 280: ...y configured as LSE oscillator pins OSC32_IN and OSC32_OUT when the LSE oscillator is ON This is done by setting the LSEON bit in the RCC_BDCR register The LSE has priority over the GPIO function Note...

Страница 281: ...s follows TAMP1INSEL is used to select which pin is used as the RTC_TAMP1 tamper input TSINSEL is used to select which pin is used as the RTC_TS time stamp input ALARMOUTTYPE is used to select whether...

Страница 282: ...me stamp enabled TAMP1INSEL TAMPER1 pin selection TSINSEL TIMESTAMP pin selection ALARMOUTTYPE RTC_ALARM configuration TAMPER1 input floating 1 0 1 Don t care Don t care TIMESTAMP and TAMPER1 input fl...

Страница 283: ...0 MODER9 1 0 MODER8 1 0 rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 MODER7 1 0 MODER6 1 0 MODER5 1 0 MODER4 1 0 MODER3 1 0 MODER2 1 0 MODER1 1 0 MODER0 1 0 rw...

Страница 284: ...8 7 6 5 4 3 2 1 0 OSPEEDR7 1 0 OSPEEDR6 1 0 OSPEEDR5 1 0 OSPEEDR4 1 0 OSPEEDR3 1 0 OSPEEDR2 1 0 OSPEEDR1 1 0 OSPEEDR0 1 0 rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw Bits 2y 2y 1 OSPEEDRy 1 0 Port...

Страница 285: ...IDR12 IDR11 IDR10 IDR9 IDR8 IDR7 IDR6 IDR5 IDR4 IDR3 IDR2 IDR1 IDR0 r r r r r r r r r r r r r r r r Bits 31 16 Reserved must be kept at reset value Bits 15 0 IDRy Port input data y 0 15 These bits ar...

Страница 286: ...0 0000 Access 32 bit word only read write register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 BR15 BR14 BR13 BR12 BR11 BR10 BR9 BR8 BR7 BR6 BR5 BR4 BR3 BR2 BR1 BR0 w w w w w w w w w w w w w w w w...

Страница 287: ...K 15 0 must not change Any error in the lock sequence aborts the lock After the first lock sequence on any bit of the port any read access on the LCKK bit will return 1 until the next CPU reset Bits 1...

Страница 288: ...AF13 1110 AF14 1111 AF15 Table 39 GPIO register map and reset values Offset Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0x00 GPIOA_ MODER MODER15 1 0...

Страница 289: ...PUPDR2 1 0 PUPDR1 1 0 PUPDR0 1 0 Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0x0C GPIOx_PUPDR where x C I J K PUPDR15 1 0 PUPDR14 1 0 PUPDR13 1 0 PUPDR12 1 0 PUPDR11 1...

Страница 290: ...AFRH where x A I J AFRH15 3 0 AFRH14 3 0 AFRH13 3 0 AFRH12 3 0 AFRH11 3 0 AFRH10 3 0 AFRH9 3 0 AFRH8 3 0 Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Table 39 GPIO regis...

Страница 291: ...when the supply voltage ranges from 2 4 to 3 6 V 9 2 SYSCFG registers for STM32F405xx 07xx and STM32F415xx 17xx 9 2 1 SYSCFG memory remap register SYSCFG_MEMRMP This register is used for specific con...

Страница 292: ...0 0000 10 FSMC Bank1 NOR PSRAM 1 and 2 mapped at 0x0000 0000 11 Embedded SRAM SRAM1 mapped at 0x0000 0000 Note Refer to Section 2 3 Memory map for details about the memory mapping at address 0x0000 00...

Страница 293: ...3 2 1 0 EXTI3 3 0 EXTI2 3 0 EXTI1 3 0 EXTI0 3 0 rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw Bits 31 16 Reserved must be kept at reset value Bits 15 0 EXTIx 3 0 EXTI x configuration x 0 to 3 These...

Страница 294: ...pin 0010 PC x pin 0011 PD x pin 0100 PE x pin 0101 PF x pin 0110 PG x pin 0111 PH x pin 1000 PI x pin 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 EXT...

Страница 295: ...Bits 15 0 EXTIx 3 0 EXTI x configuration x 12 to 15 These bits are written by software to select the source input for the EXTIx external interrupt 0000 PA x pin 0001 PB x pin 0010 PC x pin 0011 PD x p...

Страница 296: ...register takes the value 0x00 Other bits are used to swap FMC SDRAM Bank 1 2 with FMC Bank 3 4 and configure the Flash Bank 1 2 mapping Table 40 SYSCFG register map and reset values STM32F405xx 07xx...

Страница 297: ...remap 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved SWP_FMC Res FB_ MODE Reserved MEM_MODE 2 0 rw rw rw rw rw rw Bits 31 12 Reserved must be...

Страница 298: ...0 0000 After reset these bits take the value selected by the Boot pins except for FMC 000 Main Flash memory mapped at 0x0000 0000 001 System Flash memory mapped at 0x0000 0000 010 FMC Bank1 NOR PSRAM...

Страница 299: ...he same time and the sampling times differ These bits must not be set when the ADCDC1 bit is set in PWR_CR register Bits 15 0 Reserved must be kept at reset value 31 30 29 28 27 26 25 24 23 22 21 20 1...

Страница 300: ...EXTI6 3 0 EXTI5 3 0 EXTI4 3 0 rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw Bits 31 16 Reserved must be kept at reset value Bits 15 0 EXTIx 3 0 EXTI x configuration x 4 to 7 These bits are written...

Страница 301: ...x pin 0101 PF x pin 0110 PG x pin 0111 PH x pin 1000 PI x pin 1001 PJ x pin Note PK 11 8 are not used 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 EX...

Страница 302: ...0 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved READY Reserved CMP_PD r rw Bits 31 9 Reserved must be kept at reset value Bit 8 READY Compensation cell ready flag 0 I O compensat...

Страница 303: ...MC Reserved FB_MODE Reserved MEM_ MODE Reset value 0 0 0 x x x 0x04 SYSCFG_PMC Reserved MII_RMII_SEL Reserved ADC3DC2 ADC2DC2 ADC1DC2 Reserved Reset value 0 0 0 0 0x08 SYSCFG_EXTICR1 Reserved EXTI3 3...

Страница 304: ...ess requests from one or more peripherals Each stream can have up to 8 channels requests in total And each has an arbiter for handling the priority between DMA requests 10 2 DMA main features The main...

Страница 305: ...A requests The number of data items to be transferred can be managed either by the DMA controller or by the peripheral DMA flow controller the number of data items to be transferred is software progra...

Страница 306: ...llow memory to memory transfers the AHB peripheral port must also have access to the memories The AHB slave port is used to program the DMA controller it supports only 32 bit accesses See Figure 33 an...

Страница 307: ...ed to the bus matrix like DMA2 controller As a result only DMA2 streams are able to perform memory to memory transfers 3 6 CONTROLLER PERIPH RBITER MEMORY CONTROLLER MEMORY US MATRIX RBITER PERIPH 00...

Страница 308: ...rammable Each DMA transfer consists of three operations A loading from the peripheral data register or a location in memory addressed through the DMA_SxPAR or DMA_SxM0AR register A storage of the data...

Страница 309: ...5 Channel selection The 8 requests from the peripherals TIM ADC SPI I2C etc are independently connected to each channel and their connection depends on the product implementation See the following tab...

Страница 310: ...DAC2 I2C2_TX 1 These requests are available on STM32F42xxx and STM32F43xxx only Table 42 DMA1 request mapping continued Peripheral requests Stream 0 Stream 1 Stream 2 Stream 3 Stream 4 Stream 5 Strea...

Страница 311: ...egister and offers three possibilities memory to peripheral peripheral to memory or memory to memory transfers Table 44 describes the corresponding source and destination addresses When the data width...

Страница 312: ...FO is fully reloaded with data from the memory The transfer stops once the DMA_SxNDTR register reaches zero when the peripheral requests the end of transfers in case of a peripheral flow controller or...

Страница 313: ...he transfer stops once the DMA_SxNDTR register reaches zero or when the EN bit in the DMA_SxCR register is cleared by software The stream has access to the AHB source or destination port only if the a...

Страница 314: ..._SxCR register In order to optimize the packing operation it is possible to fix the increment offset size for the peripheral address whatever the size of the data transferred on the AHB peripheral por...

Страница 315: ...he Double buffer mode is enabled by setting the DBM bit in the DMA_SxCR register A double buffer stream works as a regular single buffer stream with the difference that it has two memory pointers When...

Страница 316: ...ransferred is equal to 2 NDT The DMA controller only copes with little endian addressing for both source and destination This is described in Table 46 Packing unpacking endian behavior bit PINC MINC 1...

Страница 317: ...B1 7 0 0x2 B2 7 0 0x3 B3 7 0 1 2 3 4 0x0 B0 7 0 0x4 B1 7 0 0x8 B2 7 0 0xC B3 7 0 0x0 B0 7 0 0x1 B1 7 0 0x2 B2 7 0 0x3 B3 7 0 8 16 2 1 2 3 4 0x0 B0 7 0 0x1 B1 7 0 0x2 B2 7 0 0x3 B3 7 0 1 2 0x0 B1 B0 1...

Страница 318: ...burst transfers each DMA request generates 4 8 or 16 beats of byte half word or word transfers depending on the PBURST 1 0 and PSIZE 1 0 bits in the DMA_SxCR register The same as above has to be cons...

Страница 319: ...the DMA_HISR or DMA_LISR register will be generated when the stream is enabled then the stream will be automatically disabled The allowed and forbidden configurations are described in the Source byte...

Страница 320: ...action was requested during the DMA stream configuration Note When burst transfers are requested on the peripheral AHB port and the FIFO is used DMDIS 1 in the DMA_SxCR register it is mandatory to res...

Страница 321: ...s in DMA_SxCR register are set to configure the stream to manage burst on the AHB memory port single transactions will be generated to complete the FIFO flush Direct mode By default the FIFO operates...

Страница 322: ...was stopped There is no particular action to do except to clear the EN bit in the DMA_SxCR register to disable the stream The stream may take time to be disabled ongoing transfer is completed first Th...

Страница 323: ...stream is switched off and the FIFO flush is triggered in the case of a peripheral to memory DMA transfer The TCIFx flag of the corresponding stream is set in the status register to indicate the DMA c...

Страница 324: ...the case of a double buffer mode The data will be written to or read from this memory after the peripheral event 4 Configure the total number of data items to be transferred in the DMA_SxNDTR registe...

Страница 325: ...e buffer mode FIFO error the FIFO error interrupt flag FEIFx is set if A FIFO underrun condition is detected A FIFO overrun condition is detected no detection in memory to memory mode because requests...

Страница 326: ...ot acknowledged by the stream until the overrun or underrun condition is cleared If this acknowledge takes too much time the peripheral itself may detect an overrun or underrun condition of its intern...

Страница 327: ...ts 26 20 10 4 HTIFx Stream x half transfer interrupt flag x 3 0 This bit is set by hardware It is cleared by software writing 1 to the corresponding bit in the DMA_LIFCR register 0 No half transfer ev...

Страница 328: ...rrupt flag x 7 4 This bit is set by hardware It is cleared by software writing 1 to the corresponding bit in the DMA_HIFCR register 0 No half transfer event on stream x 1 A half transfer event occurre...

Страница 329: ...esponding TEIFx flag in the DMA_LISR register Bits 24 18 8 2 CDMEIFx Stream x clear direct mode error interrupt flag x 3 0 Writing 1 to this bit clears the corresponding DMEIFx flag in the DMA_LISR re...

Страница 330: ...rw rw rw rw rw Bits 31 28 Reserved must be kept at reset value Bits 27 25 CHSEL 2 0 Channel selection These bits are set and cleared by software 000 channel 0 selected 001 channel 1 selected 010 chann...

Страница 331: ...crement offset size This bit is set and cleared by software 0 The offset size for the peripheral address calculation is linked to the PSIZE 1 The offset size for the peripheral address calculation is...

Страница 332: ...by software 00 Peripheral to memory 01 Memory to peripheral 10 Memory to memory 11 reserved These bits are protected and can be written only if EN is 0 Bit 5 PFCTRL Peripheral flow controller This bit...

Страница 333: ...responding to the stream in DMA_LISR or DMA_HISR register must be cleared 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 NDT 15 0 rw rw rw rw rw rw rw r...

Страница 334: ...heral data register from to which the data will be read written These bits are write protected and can be written only when bit EN 0 in the DMA_SxCR register 31 30 29 28 27 26 25 24 23 22 21 20 19 18...

Страница 335: ...These bits are write protected They can be written only if the stream is disabled bit EN 0 in the DMA_SxCR register or the stream is enabled EN 1 in DMA_SxCR register and bit CT 0 in the DMA_SxCR regi...

Страница 336: ...rdware 0 Direct mode enabled 1 Direct mode disabled This bit is protected and can be written only if EN is 0 This bit is set by hardware if the memory to memory mode is selected DIR bit in DMA_SxCR ar...

Страница 337: ...rved CTCIF7 CHTIF7 CTEIF7 CDMEIF7 Reserved CFEIF7 CTCIF6 CHTIF6 CTEIF6 CDMEIF6 Reserved CFEIF6 Reserved CTCIF5 CHTIF5 CTEIF5 CDMEIF5 Reserved CFEIF5 CTCIF4 CHTIF4 CTEIF4 CDMEIF4 Reserved CFEIF4 Reset...

Страница 338: ...0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0x004C DMA_S2M0AR M0A 31 0 Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0x0050 DMA_S2M1AR M1A 31 0 Reset value 0 0 0 0 0...

Страница 339: ...0 ACK CT DBM PL 1 0 PINCOS MSIZE 1 0 PSIZE 1 0 MINC PINC CIRC DIR 1 0 PFCTRL TCIE HTIE TEIE DMEIE EN Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0x008C DMA_S5NDTR Reserved NDT...

Страница 340: ...R 1 0 PFCTRL TCIE HTIE TEIE DMEIE EN Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0x00BC DMA_S7NDTR Reserved NDT 15 Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0x00C0 DMA_S7PAR PA...

Страница 341: ...hole of a source image into a part or the whole of a destination image Copying a part or the whole of a source image into a part or the whole of a destination image with a pixel format conversion Blen...

Страница 342: ...ndwidth 4 operating modes register to memory memory to memory memory to memory with pixel format conversion and memory to memory with pixel format conversion and blending Area filling with a fixed col...

Страница 343: ...isable the DMA2D interrupt Start suspend abort ongoing data transfers 11 3 3 DMA2D foreground and background FIFOs The DMA2D foreground FG FG FIFO and background BG FIFO fetch the input data to be cop...

Страница 344: ...tes in memory to memory operation with pixel format conversion no blending operation the BG FIFO is not activated 11 3 4 DMA2D foreground and background pixel format converter PFC DMA2D foreground pix...

Страница 345: ...is fixed and is defined in the DMA2D_FGCOLR for foreground pixels and in the DMA2D_BGCOLR register for background pixels The order of the fields in the system memory is defined in Table 53 Data order...

Страница 346: ...round CLUT or DMA2D_BGCMAR register background CLUT b Program the CLUT size in the CS 7 0 field of the DMA2D_FGPFCCR register foreground CLUT or DMA2D_BGPFCCR register background CLUT c Set the START...

Страница 347: ...11 3 7 DMA2D output PFC The output PFC performs the pixel format conversion from 32 bits to the output format defined in the CM 2 0 field of the DMA2D output pixel format converter configuration regis...

Страница 348: ...ored into the memory in the order defined in Table 58 Data order in memory The RGB888 aligned on 32 bit is supported through the ARGB8888 mode 11 3 9 DMA2D AHB master port timer An 8 bit timer is embe...

Страница 349: ...iguration Both source and destination data transfers can target peripherals and memories in the whole 4 Gbyte memory area at addresses ranging between 0x0000 0000 and 0xFFFF FFFF The DMA2D can operate...

Страница 350: ...CLUT loading by setting the START bit of the DMA2D_FGPFCCR register Once the CLUT loading is complete the CTCIF flag of the DMA2D_IFR register is raised and an interrupt is generated if the CTCIE bit...

Страница 351: ...bits by their respective PFCs they are blended according to the equation below The resulting 32 bit pixel value is encoded by the output PFC according to the specified output format and the data are w...

Страница 352: ...ts of DMA2D_BGOR odd while CM of DMA2D_BGPFCCR is A4 or L4 Memory transfer except in memory to memory mode MA bits in DMA2D_OMAR are not aligned with CM bits in DMA2D_OPFCCR Memory transfer except in...

Страница 353: ...their own interrupt enable flag in the DMA2D_CR register to generate an interrupt if need be TEIE and CAEIE 11 3 15 AHB dead time To limit the AHB bandwidth usage a dead time between two consecutive A...

Страница 354: ...eset value Bits 17 16 MODE DMA2D mode This bit is set and cleared by software It cannot be modified while a transfer is ongoing 00 Memory to memory FG fetch only 01 Memory to memory with PFC FG fetch...

Страница 355: ...automatically reset by hardware when the START bit is reset 0 No transfer abort requested 1 Transfer abort requested Bit 1 SUSP Suspend This bit can be used to suspend the current transfer This bit is...

Страница 356: ...rogrammed Bit 4 CTCIF CLUT transfer complete interrupt flag This bit is set when the CLUT copy from a system memory area to the internal DMA2D memory is complete Bit 3 CAEIF CLUT access error interrup...

Страница 357: ...o 1 clears the CEIF flag in the DMA2D_ISR register Bit 4 CCTCIF Clear CLUT transfer complete interrupt flag Programming this bit to 1 clears the CTCIF flag in the DMA2D_ISR register Bit 3 CAECIF Clear...

Страница 358: ...started this register is read only The address alignment must match the image format selected e g a 32 bit per pixel format must be 32 bit aligned a 16 bit per pixel format must be 16 bit aligned and...

Страница 359: ...ta transfers are disabled Once a data transfer has started this register is read only The address alignment must match the image format selected e g a 32 bit per pixel format must be 32 bit aligned a...

Страница 360: ...ey become read only Bits 23 18 Reserved must be kept at reset value Bits 17 16 AM 1 0 Alpha mode These bits select the alpha channel value to be used for the foreground image They can only be written...

Страница 361: ...n already ongoing data transfer or automatic background CLUT transfer Bit 4 CCM CLUT color mode This bit defines the color format of the CLUT It can only be written when the transfer is disabled Once...

Страница 362: ...Red Value These bits defines the red value for the A4 or A8 mode of the foreground image They can only be written when data transfers are disabled Once the transfer has started they are read only Bit...

Страница 363: ...n when data transfers are disabled Once the transfer has started they are read only Bits 23 18 Reserved must be kept at reset value Bits 17 16 AM 1 0 Alpha mode These bits define which alpha channel v...

Страница 364: ...y on going data transfer or automatic BackGround CLUT transfer Bit 4 CCM CLUT Color mode These bits define the color format of the CLUT This register can only be written when the transfer is disabled...

Страница 365: ...Bits 15 8 GREEN 7 0 Green Value These bits define the green value for the A4 or A8 mode of the background These bits can only be written when data transfers are disabled Once the transfer has started...

Страница 366: ...ddress of the data used for the CLUT address dedicated to the background image This register can only be written when no transfer is on going Once the CLUT transfer has started this register is read o...

Страница 367: ...e the alpha channel of the output color These bits can only be written when data transfers are disabled Once the transfer has started they are read only Bits 23 16 RED 7 0 Red Value These bits define...

Страница 368: ...rw rw rw rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 MA 15 0 rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw Bits 31 0 MA 31 0 Memory Address Address of the data used for the output FIFO These bits c...

Страница 369: ...ess of the next line These bits can only be written when data transfers are disabled Once the transfer has started they are read only 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved PL 13 0 r...

Страница 370: ...allow to configure the line watermark for interrupt generation An interrupt is raised when the last pixel of the watermarked line has been transferred These bits can only be written when data transfer...

Страница 371: ...eset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0x001C DMA2D_FGPFCCR ALPHA 7 0 Reserved AM 1 0 CS 7 0 Res START CCM CM 3 0 Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0x0020 DMA2D_FGCOLR APLHA...

Страница 372: ...ed DT 7 0 Reserved EN Reset value 0 0 0 0 0 0 0 0 0 0x0050 Ox03FF Reserved 0x0400 0x07FF DMA2D_FGCLUT APLHA 7 0 255 0 RED 7 0 255 0 GREEN 7 0 255 0 BLUE 7 0 255 0 Reset value X X X X X X X X X X X X X...

Страница 373: ...d efficient processing of late arriving interrupts All interrupts including the core exceptions are managed by the NVIC For more information on exceptions and NVIC programming refer to programming man...

Страница 374: ...Monitor Debug Monitor 0x0000 0030 Reserved 0x0000 0034 5 settable PendSV Pendable request for system service 0x0000 0038 6 settable SysTick System tick timer 0x0000 003C 0 7 settable WWDG Window Watch...

Страница 375: ...terrupt 0x0000 00A0 25 32 settable TIM1_UP_TIM10 TIM1 Update interrupt and TIM10 global interrupt 0x0000 00A4 26 33 settable TIM1_TRG_COM_TIM11 TIM1 Trigger and Commutation interrupts and TIM11 global...

Страница 376: ...rrupt 0x0000 0108 51 58 settable SPI3 SPI3 global interrupt 0x0000 010C 52 59 settable UART4 UART4 global interrupt 0x0000 0110 53 60 settable UART5 UART5 global interrupt 0x0000 0114 54 61 settable T...

Страница 377: ...global interrupt 0x0000 0168 75 82 settable OTG_HS_EP1_IN USB On The Go HS End Point 1 In global interrupt 0x0000 016C 76 83 settable OTG_HS_WKUP USB On The Go HS Wakeup through EXTI interrupt 0x0000...

Страница 378: ...up interrupt through the EXTI line 0x0000 004C 4 11 settable FLASH Flash global interrupt 0x0000 0050 5 12 settable RCC RCC global interrupt 0x0000 0054 6 13 settable EXTI0 EXTI Line0 interrupt 0x0000...

Страница 379: ...obal interrupt 0x0000 00B4 30 37 settable TIM4 TIM4 global interrupt 0x0000 00B8 31 38 settable I2C1_EV I2 C1 event interrupt 0x0000 00BC 32 39 settable I2C1_ER I2 C1 error interrupt 0x0000 00C0 33 40...

Страница 380: ...l interrupt 0x0000 0120 57 64 settable DMA2_Stream1 DMA2 Stream1 global interrupt 0x0000 0124 58 65 settable DMA2_Stream2 DMA2 Stream2 global interrupt 0x0000 0128 59 66 settable DMA2_Stream3 DMA2 Str...

Страница 381: ...TG_HS_WKUP USB On The Go HS Wakeup through EXTI interrupt 0x0000 0170 77 84 settable OTG_HS USB On The Go HS global interrupt 0x0000 0174 78 85 settable DCMI DCMI global interrupt 0x0000 0178 79 86 se...

Страница 382: ...hen the CPU resumes from WFE it is not necessary to clear the peripheral interrupt pending bit or the NVIC IRQ channel pending bit as the pending bit corresponding to the event line is not set To use...

Страница 383: ...re the 23 lines as interrupt sources use the following procedure Configure the mask bits of the 23 interrupt lines EXTI_IMR Configure the Trigger selection bits of the interrupt lines EXTI_RTSR and EX...

Страница 384: ...PIOs STM32F42xxx and STM32F43xxx are connected to the 16 external interrupt event lines in the following manner Figure 42 External interrupt event GPIO mapping STM32F405xx 07xx and STM32F415xx 17xx 0...

Страница 385: ...vent EXTI line 18 is connected to the USB OTG FS Wakeup event EXTI line 19 is connected to the Ethernet Wakeup event EXTI line 20 is connected to the USB OTG HS configured in FS Wakeup event EXTI line...

Страница 386: ...MR13 MR12 MR11 MR10 MR9 MR8 MR7 MR6 MR5 MR4 MR3 MR2 MR1 MR0 rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw Bits 31 23 Reserved must be kept at reset value Bits 22 0 MRx Interrupt mask on line x 0 In...

Страница 387: ...ne In this configuration both generate a trigger condition 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved TR22 TR21 TR20 TR19 TR18 TR17 TR16 rw rw rw rw rw rw rw 15 14 13 12 11 10 9 8 7 6 5...

Страница 388: ...are enabled on line x in the EXTI_IMR register writing 1 to SWIERx bit when it is set at 0 sets the corresponding pending bit in the EXTI_PR register thus resulting in an interrupt request generation...

Страница 389: ...10 9 8 7 6 5 4 3 2 1 0 0x00 EXTI_IMR Reserved MR 22 0 Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0x04 EXTI_EMR Reserved MR 22 0 Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0...

Страница 390: ...bit 8 bit or 6 bit configurable resolution Interrupt generation at the end of conversion end of injected conversion and in case of analog watchdog or overrun events Single and continuous conversion m...

Страница 391: ...DocID018909 Rev 11 391 1731 RM0090 Analog to digital converter ADC 434 13 3 ADC functional description Figure 44 shows a single ADC block diagram and Table 65 gives the ADC pin description...

Страница 392: ...TS LAGS ENABLE BITS 7 NALOG WATCHDOG EVENT 6 633 62 62 NTERRUPT 84 4 ROM PRESCALER BITS ND OF CONVERSION CHANNELS NJECTED CHANNELS ND OF INJECTED CONVERSION 7 UP TO UP TO 2EGULAR DATA REGISTER X BITS...

Страница 393: ...It is possible to organize the conversions in two groups regular and injected A group consists of a sequence of conversions that can be done on any channel and in any order For instance it is possibl...

Страница 394: ...AT conversion is performed The internal reference voltage VREFINT is connected to ADC1_IN17 The VBAT channel connected to channel ADC1_IN18 can also be converted as an injected or regular channel Note...

Страница 395: ...DC needs a stabilization time of tSTAB before it starts converting accurately After the start of the ADC conversion and after 15 clock cycles the EOC flag is set and the 16 bit ADC data register conta...

Страница 396: ...et the direct memory access DMA controller is used to transfer the data converted from the regular group of channels stored in the ADC_DR register to SRAM after each regular channel conversion The EOC...

Страница 397: ...ing timing diagram Note When using triggered injection one must ensure that the interval between trigger events is longer than the injection sequence For instance if the sequence length is 30 ADC cloc...

Страница 398: ...mode no rollover occurs When all subgroups are converted the next trigger starts the conversion of the first subgroup In the example above the 4th trigger reconverts the channels 0 1 and 2 in the 1st...

Страница 399: ...ive value The SEXT bit represents the extended sign value For channels in a regular group no offset is subtracted so only twelve bits are significant Figure 48 Right alignment of 12 bit data Figure 49...

Страница 400: ...EXTI line If the EXTEN 1 0 control bits for a regular conversion or JEXTEN 1 0 bits for an injected conversion are different from 0b00 then external events are able to trigger a conversion with the se...

Страница 401: ...urce Type EXTSEL 3 0 TIM1_CH1 event Internal signal from on chip timers 0000 TIM1_CH2 event 0001 TIM1_CH3 event 0010 TIM2_CH2 event 0011 TIM2_CH3 event 0100 TIM2_CH4 event 0101 TIM2_TRGO event 0110 TI...

Страница 402: ...er conversion by reducing the ADC resolution The RES bits are used to select the number of bits available in the data register The minimum conversion time for each resolution is then as follows 12 bit...

Страница 403: ...ocked after the last valid data have been transferred which means that all the data transferred to the RAM can be considered as valid At the end of the last DMA transfer number of transfers configured...

Страница 404: ...sly by the ADC1 master to the ADC2 and ADC3 slaves depending on the mode selected by the MULTI 4 0 bits in the ADC_CCR register Note In multi ADC mode when configuring conversion trigger by an externa...

Страница 405: ...l ADC mode the ADC common data register ADC_CDR contains both the ADC1 and ADC2 s regular converted data All 32 register bits are used X X X 0 0ORTS DDRESS DATA BUS 84 84 NJECTED DATA REGISTERS X BITS...

Страница 406: ...equest two data items are available two half words representing two ADC converted data items are transferred as a word In Dual ADC mode both ADC2 and ADC1 data are transferred on the first request ADC...

Страница 407: ...3 in triple mode only the DMA requests are no longer issued to ensure that all the data transferred to the RAM are valid It may happen that the EOC bit corresponding to one ADC remains set because the...

Страница 408: ...annels triple ADC mode 13 9 2 Regular simultaneous mode This mode is performed on a regular group of channels The external trigger source comes from the regular group multiplexer of ADC1 selected by t...

Страница 409: ...e 54 Regular simultaneous mode on 16 channels dual ADC mode Triple ADC mode At the end of conversion event on ADC1 ADC2 or ADC3 Three 32 bit DMA transfer requests are generated if DMA 1 0 bits in the...

Страница 410: ...terrupted for instance when DMA end of transfer occurs the multi ADC sequencer must be reset by configuring it in independent mode first bits DUAL 4 0 00000 before reprogramming the interleaved mode A...

Страница 411: ...al to 0b10 The request first transfers the first converted data stored in the lower half word of the ADC_CDR 32 bit register to SRAM then it transfers the second converted data stored in ADC_CDR s upp...

Страница 412: ...els in the group have been converted A JEOC interrupt if enabled is generated after all injected ADC2 channels in the group have been converted If another external trigger occurs after all injected ch...

Страница 413: ...ed If another external trigger occurs after all injected channels in the group have been converted then the alternate trigger process restarts by converting the injected ADC1 channels in the group Fig...

Страница 414: ...synchronously at the end of the injected conversion Note In combined regular simultaneous alternate trigger mode one must convert sequences with the same length or ensure that the interval between tr...

Страница 415: ...e input channel ADC1_IN18 as VBAT ADC1_IN18 is used to convert the sensor output voltage or VBAT into a digital value Only one conversion temperature sensor or VBAT must be selected at a time When the...

Страница 416: ...ta register 8 Calculate the temperature using the following formula Temperature in C VSENSE V25 Avg_Slope 25 Where V25 VSENSE value for 25 C Avg_Slope average slope of the temperature vs VSENSE curve...

Страница 417: ...M32F42xx and STM32F43xx devices VBAT and temperature sensor are connected to the same ADC internal channel ADC1_IN18 Only one conversion either temperature sensor or VBAT must be selected at a time Wh...

Страница 418: ...nnel conversion starts It is cleared by software 0 No regular channel conversion started 1 Regular channel conversion has started Bit 3 JSTRT Injected channel start flag This bit is set by hardware wh...

Страница 419: ...01 10 bit 13 ADCCLK cycles 10 8 bit 11 ADCCLK cycles 11 6 bit 9 ADCCLK cycles Bit 23 AWDEN Analog watchdog enable on regular channels This bit is set and cleared by software 0 Analog watchdog disable...

Страница 420: ...t At the end of each regular group sequence if the EOCS bit is cleared to 0 At the end of each regular channel conversion if the EOCS bit is set to 1 Note A JEOC interrupt is generated only on the end...

Страница 421: ...on is launched Bits 29 28 EXTEN External trigger enable for regular channels These bits are set and cleared by software to select the external trigger polarity and enable the trigger of a regular grou...

Страница 422: ...3 CC2 event 0101 Timer 3 CC4 event 0110 Timer 4 CC1 event 0111 Timer 4 CC2 event 1000 Timer 4 CC3 event 1001 Timer 4 TRGO event 1010 Timer 5 CC4 event 1011 Timer 5 TRGO event 1100 Timer 8 CC2 event 1...

Страница 423: ...d SMP18 2 0 SMP17 2 0 SMP16 2 0 SMP15 2 1 rw rw rw rw rw rw rw rw rw rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 SMP15_0 SMP14 2 0 SMP13 2 0 SMP12 2 0 SMP11 2 0 SMP10 2 0 rw rw rw rw rw rw rw rw rw rw...

Страница 424: ...les 110 144 cycles 111 480 cycles 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved JOFFSETx 11 0 rw rw rw rw rw rw rw rw rw rw rw rw Bits 31 12 R...

Страница 425: ...28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved L 3 0 SQ16 4 1 rw rw rw rw rw rw rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 SQ16_0 SQ15 4 0 SQ14 4 0 SQ13 4 0 rw rw rw rw rw rw rw rw rw rw rw rw rw B...

Страница 426: ...n regular sequence Bits 19 15 SQ10 4 0 10th conversion in regular sequence Bits 14 10 SQ9 4 0 9th conversion in regular sequence Bits 9 5 SQ8 4 0 8th conversion in regular sequence Bits 4 0 SQ7 4 0 7t...

Страница 427: ...L 1 0 JSQ4 4 1 rw rw rw rw rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 JSQ4 0 JSQ3 4 0 JSQ2 4 0 JSQ1 4 0 rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw Bits 31 22 Reserved must be kept at reset value...

Страница 428: ...right aligned as shown in Figure 48 and Figure 49 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 DATA 15 0 r r r r r r r r r r r r r r r r Bits 31 16 Re...

Страница 429: ...ster Bit 11 JSTRT2 Injected channel Start flag of ADC2 This bit is a copy of the JSTRT bit in the ADC2_SR register Bit 10 JEOC2 Injected channel end of conversion of ADC2 This bit is a copy of the JEO...

Страница 430: ...must be kept at reset value Bits 17 16 ADCPRE ADC prescaler Set and cleared by software to select the frequency of the clock to the ADC The clock is common for all the ADCs Note 00 PCLK2 divided by 2...

Страница 431: ...de 00010 Combined regular simultaneous alternate trigger mode 00011 Reserved 00101 Injected simultaneous mode only 00110 Regular simultaneous mode only 00111 interleaved mode only 01001 Alternate trig...

Страница 432: ...Refer to Dual ADC mode In triple mode these bits contain alternatively the regular data of ADC2 ADC1 and ADC3 Refer to Triple ADC mode Bits 15 0 DATA1 15 0 1st data item of a pair of regular conversi...

Страница 433: ...Reserved HT 11 0 Reset value 1 1 1 1 1 1 1 1 1 1 1 1 0x28 ADC_LTR Reserved LT 11 0 Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0x2C ADC_SQR1 Reserved L 3 0 Regular channel sequence SQx_x bits Reset value 0 0...

Страница 434: ...7 6 5 4 3 2 1 0 0x00 ADC_CSR Reserved OVR STRT JSTRT JEOC EOC AWD Reser ved OVR STRT JSTRT JEOC EOC AWD Reser ved OVR STRT JSTRT JEOC EOC AWD Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADC3 ADC2...

Страница 435: ...ual DAC channel mode conversions could be done independently or simultaneously when both channels are grouped together for synchronous update operations An input reference pin VREF shared with ADC is...

Страница 436: ...marks VREF Input analog reference positive The higher positive reference voltage for the DAC 1 8 V VREF VDDA VDDA Input analog supply Analog power supply VSSA Input analog supply ground Ground for ana...

Страница 437: ...corresponding BOFFx bit in the DAC_CR register 14 3 3 DAC data format Depending on the selected configuration mode the data have to be written into the specified register as described below Single DAC...

Страница 438: ...rnal non memory mapped registers The DHR1 and DHR2 registers are then loaded into the DOR1 and DOR2 registers respectively either automatically by software trigger or by an external event trigger Figu...

Страница 439: ...a rising edge on the selected timer TRGO output or on the selected external interrupt line 9 the last data stored into the DAC_DHRx register are transferred into the DAC_DORx register The DAC_DORx reg...

Страница 440: ...r the first external trigger is received first request then no new request is issued and the DMA channelx underrun flag DMAUDRx in the DAC_SR register is set reporting the error condition DMA data tra...

Страница 441: ...tion It is possible to add a small amplitude triangular waveform on a DC or slowly varying signal DAC triangle wave generation is selected by setting WAVEx 1 0 to 10 The amplitude is configured throug...

Страница 442: ...drive both DAC channels at the same time Eleven possible conversion modes are possible using the two DAC channels and these dual registers All the conversion modes can nevertheless be obtained using s...

Страница 443: ...ted When a DAC channel2 trigger arrives the LFSR2 counter with the same mask is added to the DHR2 register and the sum is transferred into DAC_DOR2 three APB1 clock cycles later Then the LFSR2 counter...

Страница 444: ...nfigure the DAC in this conversion mode the following sequence is required Set the two DAC channel trigger enable bits TEN1 and TEN2 Configure different trigger sources by setting different values in...

Страница 445: ...rrives the LFSR1 counter with the same mask is added to the DHR1 register and the sum is transferred into DAC_DOR1 three APB1 clock cycles later The LFSR1 counter is then updated At the same time the...

Страница 446: ...transferred into DAC_DOR2 three APB1 clock cycles later The DAC channel2 triangle counter is then updated 14 4 11 Simultaneous trigger with different triangle generation To configure the DAC in this...

Страница 447: ...disabled 1 DAC channel2 DMA mode enabled Bits 27 24 MAMP2 3 0 DAC channel2 mask amplitude selector These bits are written by software to select mask in wave generation mode or amplitude in triangle ge...

Страница 448: ...r are transferred three APB1 clock cycles later to the DAC_DOR2 register Note When software trigger is selected the transfer from the DAC_DHRx register to the DAC_DOR2 register takes only one APB1 clo...

Страница 449: ...d 1x Triangle wave generation enabled Note Only used if bit TEN1 1 DAC channel1 trigger enabled Bits 5 3 TSEL1 2 0 DAC channel1 trigger selection These bits select the external event used to trigger D...

Страница 450: ...gger enabled Note This bit is cleared by hardware one APB1 clock cycle later once the DAC_DHR2 register value has been loaded into the DAC_DOR2 register Bit 0 SWTRIG1 DAC channel1 software trigger Thi...

Страница 451: ...1 0 Reserved rw rw rw rw rw rw rw rw rw rw rw rw Bits 31 16 Reserved must be kept at reset value Bits 15 4 DACC1DHR 11 0 DAC channel1 12 bit left aligned data These bits are written by software which...

Страница 452: ...R 11 0 DAC channel2 12 bit right aligned data These bits are written by software which specifies 12 bit data for DAC channel2 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10...

Страница 453: ...tten by software which specifies 12 bit data for DAC channel2 Bits 15 12 Reserved must be kept at reset value Bits 11 0 DACC1DHR 11 0 DAC channel1 12 bit right aligned data These bits are written by s...

Страница 454: ...gned data These bits are written by software which specifies 8 bit data for DAC channel2 Bits 7 0 DACC1DHR 7 0 DAC channel1 8 bit right aligned data These bits are written by software which specifies...

Страница 455: ...d must be kept at reset value Bit 13 DMAUDR1 DAC channel1 DMA underrun flag This bit is set by hardware and cleared by software by writing it to 1 0 No DMA underrun error condition occurred for DAC ch...

Страница 456: ...eserved DACC1DHR 11 0 0x24 DAC_ DHR12LD DACC2DHR 11 0 Reserved DACC1DHR 11 0 Reserved 0x28 DAC_ DHR8RD Reserved DACC2DHR 7 0 DACC1DHR 7 0 0x2C DAC_ DOR1 Reserved DACC1DOR 11 0 0x30 DAC_ DOR2 Reserved...

Страница 457: ...llel interface Embedded external line and frame synchronization Continuous or snapshot mode Crop feature Supports the following data formats 8 10 12 14 bit progressive video either monochrome or raw b...

Страница 458: ...by the DMA not by the camera interface The data received from the camera can be organized in lines frames raw YUB RGB Bayer modes or can be a sequence of JPEG images To enable JPEG image reception th...

Страница 459: ...d the unused data pins must not be assigned to DCMI interface through GPIO alternate functions The data are synchronous with PIXCLK and change on the rising falling edge of the pixel clock depending o...

Страница 460: ...in the MSB position in the 32 bit word as shown in Table 80 12 bit data When EDM 1 0 in DCMI_CR are programmed to 10 the camera interface captures the 12 bit data at its input D 0 11 and stores them...

Страница 461: ...ot in data Embedded synchronization codes are supported only for the 8 bit parallel data interface width that is in the DCMI_CR register the EDM 1 0 bits should be cleared to 00 For compressed data th...

Страница 462: ...es that are not used in data anymore There are 4 types of codes all with a 0xFF0000XY format The embedded synchronization codes are supported only in 8 bit parallel data width capture in the DCMI_CR r...

Страница 463: ...start code is embedded in the bit 4 of the frame start code 15 5 4 Capture modes This interface supports two types of capture snapshot single frame and continuous grab Snapshot mode single frame In t...

Страница 464: ...on mode ESS 0 in DCMI_CR the IT_VSYNC interrupt is generated if enabled even when CAPTURE 0 in DCMI_CR so to reduce the frame capture rate even further the IT_VSYNC interrupt can be used to count the...

Страница 465: ...capture while HSYNC serves as a data enable signal The number of bytes in a line may not be a multiple of 4 you should therefore be careful when handling this case since a DMA request is generated eac...

Страница 466: ...els No limit in JPEG compressed mode For monochrome RGB YCbCr the frame buffer is stored in raster mode 32 bit words are used Only the little endian format is supported Figure 80 Pixel raster scan ord...

Страница 467: ...hroma blue and red Each component is encoded in 8 bits Luma and chroma are stored together interleaved as shown in Table 85 15 7 DCMI interrupts Five interrupts are generated All interrupts are maskab...

Страница 468: ...ck 01 Interface captures 10 bit data on every pixel clock 10 Interface captures 12 bit data on every pixel clock 11 Interface captures 14 bit data on every pixel clock Bits 9 8 FCRC 1 0 Frame capture...

Страница 469: ...tured If the size of the crop window exceeds the picture size then only the picture size is captured Bit 1 CM Capture mode 0 Continuous grab mode The received data are transferred into the destination...

Страница 470: ...it gives the state of the VSYNC pin with the correct programmed polarity When embedded synchronization codes are used the meaning of this bit is the following 0 active frame 1 synchronization between...

Страница 471: ...changes from the inactive state to the active state In the case of embedded synchronization this bit is set only if the CAPTURE bit is set in DCMI_CR It is cleared by writing a 1 to the VSYNC_ISC bit...

Страница 472: ...when a line has been completely received Bit 3 VSYNC_IE VSYNC interrupt enable 0 No interrupt generation 1 An interrupt is generated on each VSYNC transition from the inactive to the active state The...

Страница 473: ...t is generated on VSYNC transitions 1 An interrupt is generated on each VSYNC transition from the inactive to the active state and the VSYNC_IE bit is set in DCMI_IER The active state of the VSYNC sig...

Страница 474: ...15 5 Reserved must be kept at reset value Bit 4 LINE_ISC line interrupt status clear Writing a 1 into this bit clears LINE_RIS in the DCMI_RIS register Bit 3 VSYNC_ISC Vertical synch interrupt status...

Страница 475: ...C is programmed to 0xFF all the unused codes 0xFF0000XY are interpreted as frame end delimiters Bits 23 16 LEC Line end delimiter code This byte specifies the code of the line end delimiter The code c...

Страница 476: ...e of the line end delimiter 0 The corresponding bit in the LEC byte in DCMI_ESCR is masked while comparing the line end delimiter with the received data 1 The corresponding bit in the LEC byte in DCMI...

Страница 477: ...be kept at reset value Bit 13 0 HOFFCNT 13 0 Horizontal offset count This value gives the number of pixel clocks to count before starting a capture 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 1...

Страница 478: ...r r r r r r r r r r r r r r r r r r r r r r r r r r r r Bits 31 24 Data byte 3 Bits 23 16 Data byte 2 Bits 15 8 Data byte 1 Bits 7 0 Data byte 0 Table 87 DCMI register map and reset values Offset Reg...

Страница 479: ...0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0x20 DCMI_CWSTR T Reserve d VST 12 0 Reserved HOFFCNT 13 0 Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0x24 DCMI_CWSIZ...

Страница 480: ...le CLUT up to 256 color 256x24 bit per layer Supports up to XGA 1024x768 resolution Programmable timings for different display panels Programmable Background color Programmable polarity for HSync VSyn...

Страница 481: ...reset and clocks The LCD TFT controller peripheral uses 3 clock domains The AHB clock domain HCLK for data transfer from the memories to the Layer FIFO The APB2 clock domain PCLK2 for register configu...

Страница 482: ...ust be connected to LCD TFT controller LCD_R 7 3 LCD_G 7 2 and LCD_B 7 3 16 4 LTDC programmable parameters The LCD TFT controller provides flexible configurable parameters It can be enabled or disable...

Страница 483: ...tive Height are configured by programming the accumulated value HSYNC Width HBP Active Width 1 and the accumulated value VSYNC Width VBP Active Height 1 in the LTDC_AWCR register only up to 1024x768 i...

Страница 484: ...01E7 TOTALH 10 0 is 0x1E7 0x4 0x2 0x1E0 1 Programmable polarity The Horizontal and Vertical Synchronization Data Enable and Pixel Clock output signals polarity can be programmed to active high or acti...

Страница 485: ...two layers can be enabled disabled and configured separately The layer display order is fixed and it is bottom up If two layers are enabled the Layer2 is the top displayed window Windowing Every layer...

Страница 486: ...565 red channel become bit positions 43210432 the 3 LSBs are filled with the 3 MSBs of the 5 bits The figure below describes the pixel data mapping depending on the selected format Table 89 Pixel Data...

Страница 487: ...y 256 colors The address of each color is configured in the CLUTADD bits in the LTDC_LxCLUTWR register In case of AL44 input pixel format the CLUT has to be only loaded by 16 colors The address of eac...

Страница 488: ...is generated if it has been previously enabled If it is set to more bytes than actually required the useless data read from the FIFO is discarded The useless data is not displayed Color Frame Buffer...

Страница 489: ...at run time to replace the pixel RGB value The Color Keying is enabled through the LTDC_LxCKCR register 16 5 LTDC interrupts The LTDC provides four maskable interrupts logically ORed to two interrupt...

Страница 490: ...The number of lines of the color frame buffer in the LTDC_LxCFBLNR register if needed load the CLUT with the RGB values and its address in the LTDC_LxCLUTWR register If needed configure the default c...

Страница 491: ...C programmable parameters for an example of configuration Address offset 0x0C Reset value 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved HSW 11 0 rw rw rw rw rw rw rw rw rw rw rw...

Страница 492: ...its of horizontal scan line These bits define the accumulated Vertical back porch width which includes the Vertical Synchronization and Vertical back porch lines minus 1 The Vertical back porch is the...

Страница 493: ...19 18 17 16 Reserved TOTALW 11 0 rw rw rw rw rw rw rw rw rw rw rw rw 16 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved TOTALH 10 0 rw rw rw rw rw rw rw rw rw rw rw Bits 31 28 Reserved must be kept at res...

Страница 494: ...8 PCPOL Pixel Clock Polarity This bit is set and cleared by software 0 input pixel clock 1 inverted input pixel clock Bits 27 17 Reserved must be kept at reset value Bit 16 DEN Dither Enable This bit...

Страница 495: ...set 0x2C Reset value 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved VBR IMR rw rw Bits 31 2 Reserved must be kept at reset value Bi...

Страница 496: ...ground blue value 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved RRIE TERRIE FUIE LIE rw rw rw rw Bits 31 4 Reserved must be kept at reset valu...

Страница 497: ...rupt generated 1 Register Reload interrupt generated when a vertical blanking reload occurs and the first line after the active area is reached Bit 2 TERRIF Transfer Error interrupt flag 0 No Transfer...

Страница 498: ...IF Clears the Transfer Error Interrupt Flag 0 No effect 1 Clears the TERRIF flag in the LTDC_ISR register Bit 1 CFUIF Clears the FIFO Underrun Interrupt flag 0 No effect 1 Clears the FUDERRIF flag in...

Страница 499: ...ed polarity in the LTDC_GCR register instead it returns the current active display phase Bits 31 16 CXPOS 15 0 Current X Position These bits return the current X position Bits 15 0 CYPOS 15 0 Current...

Страница 500: ...e allowed Address offset 0x88 0x80 x Layerx 1 Layerx 1 or 2 Reset value 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved CLUTEN Reser...

Страница 501: ...egister The last visible line of a frame is the programmed value of AAH 10 0 bits in the LTDC_AWCR register All values within this range are allowed Address offset 0x8C 0x80 x Layerx 1 Layerx 1 or 2 R...

Страница 502: ...e RGB which is used by the Color Keying Address offset 0x90 0x80 x Layerx 1 Layerx 1 or 2 Reset value 0x0000 0000 Bits 31 27 Reserved must be kept at reset value Bits 26 16 WVSPPOS 10 0 Window Vertica...

Страница 503: ...constant alpha value divided by 255 by Hardware which is used in the alpha blending Refer to LTDC_LxBFCR register Address offset 0x98 0x80 x Layerx 1 Layerx 1 or 2 Reset value Layerx 1 0x0000 00FF 31...

Страница 504: ...hese bits configure the Constant Alpha used for blending The Constant Alpha is divided by 255 by hardware Example if the programmed Constant Alpha is 0xFF the Constant Alpha value is 255 255 1 31 30 2...

Страница 505: ...8 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved BF1 2 0 Reserved BF2 2 0 rw rw rw rw rw rw Bits 31 11 Reserved must be kept at reset value Bits 10 8 BF1 2...

Страница 506: ...t to the address where the pixel data of the top left pixel of a layer is stored in the frame buffer Address offset 0xAC 0x80 x Layerx 1 Layerx 1 or 2 Reset value 0x0000 0000 16 7 23 LTDC Layerx Color...

Страница 507: ...ayer If it is configured to less bytes than required a FIFO underrun interrupt will be generated if enabled The start address and pitch settings on the other hand define the correct start of every lin...

Страница 508: ...in the LTDC_LxCR register The CLUT is only meaningful for L8 AL44 and AL88 pixel format 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 CLUTADD 7 0 RED 7 0 w w w w w w w w w w w w w w w w 15 14 13 12...

Страница 509: ...0 0 0 0 0 0 0 0 0 0 0 0 0 0 0x0018 LTDC_GCR HSPOL VSPOL DEPOL PCPOL Reserve DEN Reserved DRW 2 0 Reserved DGW 2 0 Reserved DBW 2 0 Reserved LTDCEN Reset value 0 0 0 0 0 0 1 0 0 1 0 0 1 0 0 0x0024 LTDC...

Страница 510: ...0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0x0104 LTDC_L2CR Reserved CLUTEN Reserved COLKEN LEN Reset value 0 0 0 0x0108 LTDC_L2WHPCR Reserved WHSPPOS 11 0 Reserved WHSTPOS 11 0 Rese...

Страница 511: ...e 0 0 0 0 0 0 0 0 0 0 0 0x0144 LTDC_L2CLUTWR CLUTADD 7 0 RED 7 0 GREEN 7 0 BLUE 7 0 Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Table 91 LTDC register map and reset val...

Страница 512: ...for a variety of purposes including measuring the pulse lengths of input signals input capture or generating output waveforms output compare PWM complementary PWM with dead time insertion Pulse length...

Страница 513: ...cuit to control the timer with external signals and to interconnect several timers together Repetition counter to update the timer registers only after a given number of cycles of the counter Break in...

Страница 514: ...ector IC2PS IC1PS TI1FP1 output control DTG output control DTG output control Reg event Notes Preload registers transferred to active registers on U event according to control bit interrupt DMA output...

Страница 515: ...load preload enable bit ARPE in TIMx_CR1 register The update event is sent when the counter reaches the overflow or underflow when downcounting and if the UDIS bit equals 0 in the TIMx_CR1 register It...

Страница 516: ...us one TIMx_RCR 1 Else the update event is generated at each counter overflow Setting the UG bit in the TIMx_EGR register by software or by using the slave mode controller also generates an update eve...

Страница 517: ...update flag UIF bit in TIMx_SR register is set depending on the URS bit The repetition counter is reloaded with the content of TIMx_RCR register The auto reload shadow register is updated with the pr...

Страница 518: ...t preloaded CK_PSC 0000 0001 CNT_EN Timer clock CK_CNT Counter register Update interrupt flag UIF 0035 0036 Counter overflow Update event UEV Timer clock CK_CNT Counter register 00 1F 20 Update interr...

Страница 519: ...estarts from the current auto reload value whereas the counter of the prescaler restarts from 0 but the prescale rate doesn t change In addition if the URS bit update request selection in TIMx_CR1 reg...

Страница 520: ...y 2 Figure 97 Counter timing diagram internal clock divided by 4 CK_PSC 36 CNT_EN Timer clock CK_CNT Counter register Update interrupt flag UIF Counter underflow cnt_udf Update event UEV 35 34 33 32 3...

Страница 521: ...aligned mode 1 CMS 01 the counter counts up Center aligned mode 2 CMS 10 the counter counts up and down Center aligned mode 3 CMS 11 In this mode the DIR direction bit in the TIMx_CR1 register cannot...

Страница 522: ...d the update flag UIF bit in TIMx_SR register is set depending on the URS bit The repetition counter is reloaded with the content of TIMx_RCR register The buffer of the prescaler is reloaded with the...

Страница 523: ...overflow Figure 103 Counter timing diagram internal clock divided by N CK_PSC 0002 0000 0001 0002 0003 CNT_EN Timer clock CK_CNT Counter register Update interrupt flag UIF 0003 0001 Counter underflow...

Страница 524: ...isters to the shadow registers TIMx_ARR auto reload register TIMx_PSC prescaler register but also TIMx_CCRx capture compare registers in compare mode every N 1 counter overflows or underflows where N...

Страница 525: ...e slave mode controller it occurs immediately whatever the value of the repetition counter is and the repetition counter is reloaded with the content of the TIMx_RCR register In center aligned mode fo...

Страница 526: ...ed automatically As soon as the CEN bit is written to 1 the prescaler is clocked by the internal clock CK_INT Figure 107 shows the behavior of the control circuit and the upcounter in normal mode with...

Страница 527: ...ct TI2 as the trigger input source by writing TS 110 in the TIMx_SMCR register 6 Enable the counter by writing CEN 1 in the TIMx_CR1 register Note The capture prescaler is not used for triggering so y...

Страница 528: ...zation circuit on the ETRP signal Figure 111 Control circuit in external clock mode 2 17 3 5 Capture compare channels Each Capture Compare channel is built around a capture compare register including...

Страница 529: ...8 ICPS 1 0 TI1F_ED filter ICF 3 0 downcounter TIMx_CCMR1 Edge Detector TI1F_Rising TI1F_Falling to the slave mode controller TI1FP1 11 01 TIMx_CCMR1 CC1S 1 0 IC1 TI2FP1 TRC from channel 2 from slave m...

Страница 530: ...hen a capture occurs the corresponding CCXIF flag TIMx_SR register is set and an interrupt or a DMA request can be sent if they are enabled If a capture occurs while the CCxIF flag was already high th...

Страница 531: ...nel by writing CC1P and CC1NP bits to 0 in the TIMx_CCER register rising edge in this case Program the input prescaler In our example we wish the capture to be performed at each valid transition so th...

Страница 532: ...ster TI1 selected Select the active polarity for TI1FP1 used both for capture in TIMx_CCR1 and counter clear write the CC1P and CC1NP bits to 0 active on rising edge Select the active input for TIMx_C...

Страница 533: ...ompare mode This function is used to control an output waveform or indicating when a period of time has elapsed When a match is found between the capture compare register and the counter the output co...

Страница 534: ...put compare mode toggle on OC1 17 3 10 PWM mode Pulse Width Modulation mode allows you to generate a signal with a frequency determined by the value of the TIMx_ARR register and a duty cycle determine...

Страница 535: ...er is low Refer to Section Upcounting mode on page 516 In the following example we consider PWM mode 1 The reference PWM signal OCxREF is high as long as TIMx_CNT TIMx_CCRx else it becomes low If the...

Страница 536: ...the CMS bits configuration The direction bit DIR in the TIMx_CR1 register is updated by hardware and must not be changed by software Refer to Section Center aligned mode up down counting on page 521 F...

Страница 537: ...s of level shifters delays due to power switches You can select the polarity of the outputs main output OCx or complementary OCxN independently for each output This is done by writing to the CCxP and...

Страница 538: ...be re directed to the OCx output or to OCxN output by configuring the CCxE and CCxNE bits in the TIMx_CCER register This allows you to send a specific waveform such as PWM or static active level on o...

Страница 539: ...ction before reading it correctly This is because you write the asynchronous signal and read the synchronous signal When a break occurs selected level on the break input The MOE bit is cleared asynchr...

Страница 540: ...TIMx_BDTR register By software through the BG bit of the TIMx_EGR register In addition to the break input and the output management a write protection has been implemented inside the break circuit to...

Страница 541: ...0 OISx 0 OCx OCxN not implemented CCxP 1 OISx 1 OCx OCxN not implemented CCxP 1 OISx 0 OCx OCxN CCxE 1 CCxP 0 OISx 0 CCxNE 1 CCxNP 0 OISxN 1 delay delay delay OCx OCxN CCxE 1 CCxP 0 OISx 1 CCxNE 1 CC...

Страница 542: ...his case the ETR must be configured as follow 1 The External Trigger Prescaler should be kept off bits ETPS 1 0 of the TIMx_SMCR register set to 00 2 The external clock mode 2 must be disabled bit ECE...

Страница 543: ...ent occurs COMIF bit in the TIMx_SR register which can generate an interrupt if the COMIE bit is set in the TIMx_DIER register or a DMA request if the COMDE bit is set in the TIMx_DIER register Figure...

Страница 544: ...ifferent from the counter initial value Before starting when the timer is waiting for the trigger the configuration must be In upcounting CNT CCRx ARR in particular 0 CCRx In downcounting CNT CCRx Fig...

Страница 545: ...limits the minimum delay tDELAY min we can get If you want to output a waveform with the minimum delay you can set the OCxFE bit in the TIMx_CCMRx register Then OCxRef and OCx are forced in response...

Страница 546: ...may be connected to an external interrupt input and trigger a counter reset Figure 127 gives an example of counter operation showing count signal generation and direction control It also shows how in...

Страница 547: ...s purpose Depending on the time between two events the counter can also be read at regular times You can do this by latching the counter value into a third input capture register if available then the...

Страница 548: ...ed so that a positive pulse is generated after a programmed delay in output compare or PWM mode This pulse is sent to the advanced control timer TIM1 or TIM8 through the TRGO output Example you want t...

Страница 549: ...TIM8 581 Figure 129 Example of hall sensor interface counter CNT TRGO OC2REF CCR2 OC1 OC1N COM Write CCxE CCxNE TIH1 TIH2 TIH3 CCR1 OC2 OC2N OC3 OC3N C7A3 C7A8 C794 C7A5 C7AB C796 and OCxM for next s...

Страница 550: ...capture source only CC1S 01 in the TIMx_CCMR1 register Write CC1P 0 and CC1NP 0 in TIMx_CCER register to validate the polarity and detect rising edges only Configure the timer in reset mode by writing...

Страница 551: ...validate the polarity and detect low level only Configure the timer in gated mode by writing SMS 101 in TIMx_SMCR register Select TI1 as the input source by writing TS 101 in TIMx_SMCR register Enabl...

Страница 552: ...tart of the counter is due to the resynchronization circuit on TI2 input Figure 132 Control circuit in trigger mode Slave mode external clock mode 2 trigger mode The external clock mode 2 can be used...

Страница 553: ...cuit in external clock mode 2 trigger mode 17 3 20 Timer synchronization The TIM timers are linked together internally for timer synchronization or chaining Refer to Section 18 3 15 Timer synchronizat...

Страница 554: ...ter is buffered Bits 6 5 CMS 1 0 Center aligned mode selection 00 Edge aligned mode The counter counts up or down depending on the direction bit DIR 01 Center aligned mode 1 The counter counts up and...

Страница 555: ...d registers are then loaded with their preload values 1 UEV disabled The Update event is not generated shadow registers keep their value ARR PSC CCRx However the counter and the prescaler are reinitia...

Страница 556: ...e the Counter Enable signal CNT_EN is used as trigger output TRGO It is useful to start several timers at the same time or to control a window in which a slave timer is enable The Counter Enable signa...

Страница 557: ...e COMG bit or when an rising edge occurs on TRGI Note This bit acts only on channels that have a complementary output Bit 1 Reserved must be kept at reset value Bit 0 CCPC Capture compare preloaded co...

Страница 558: ...counter is clocked by any active edge on the ETRF signal Note 1 Setting the ECE bit has the same effect as selecting external clock mode 1 with TRGI connected to ETRF SMS 111 and TS 111 2 It is possib...

Страница 559: ...0 fSAMPLING fDTS 32 N 6 1111 fSAMPLING fDTS 32 N 8 Bit 7 MSM Master slave mode 0 No action 1 The effect of an event on the trigger input TRGI is delayed to allow a perfect synchronization between the...

Страница 560: ...Both start and stop of the counter are controlled 110 Trigger Mode The counter starts at a rising edge of the trigger TRGI but it is not reset Only the start of the counter is controlled 111 External...

Страница 561: ...te DMA request enabled Bit 7 BIE Break interrupt enable 0 Break interrupt disabled 1 Break interrupt enabled Bit 6 TIE Trigger interrupt enable 0 Trigger interrupt disabled 1 Trigger interrupt enabled...

Страница 562: ...lue has been captured in TIMx_CCR1 register while CC1IF flag was already set Bit 8 Reserved must be kept at reset value Bit 7 BIF Break interrupt flag This flag is set by hardware as soon as the break...

Страница 563: ...e selected polarity Bit 0 UIF Update interrupt flag This bit is set by hardware on an update event It is cleared by software 0 No update occurred 1 Update interrupt pending This bit is set by hardware...

Страница 564: ...ed by hardware 0 No action 1 A capture compare event is generated on channel 1 If channel CC1 is configured as output CC1IF flag is set Corresponding interrupt or DMA request is sent if enabled If cha...

Страница 565: ...OC1 FE CC1S 1 0 IC2F 3 0 IC2PSC 1 0 IC1F 3 0 IC1PSC 1 0 rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw Bit 15 OC2CE Output Compare 2 clear enable Bits 14 12 OC2M 2 0 Output Compare 2 mode Bit 11 OC2...

Страница 566: ...REF level changes only when the result of the comparison changes or when the output compare mode switches from frozen mode to PWM mode 3 On channels having a complementary output this bit field is pre...

Страница 567: ...is working only if an internal trigger input is selected through TS bit TIMx_SMCR register Note CC2S bits are writable only when the channel is OFF CC2E 0 in TIMx_CCER Bits 7 4 IC1F 3 0 Input capture...

Страница 568: ...preload enable Bit 10 OC4FE Output compare 4 fast enable Bits 9 8 CC4S Capture Compare 4 selection This bit field defines the direction of the channel input output as well as the used input 00 CC4 ch...

Страница 569: ...efines the direction of the channel input output as well as the used input 00 CC3 channel is configured as output 01 CC3 channel is configured as input IC3 is mapped on TI3 10 CC3 channel is configure...

Страница 570: ...els having a complementary output this bit is preloaded If the CCPC bit is set in the TIMx_CR2 register then the CC1NP active bit takes the new value from the preloaded bit only when a Commutation eve...

Страница 571: ...is not inverted trigger operation in gated mode This configuration must not be used in encoder mode Note On channels having a complementary output this bit is preloaded If the CCPC bit is set in the...

Страница 572: ...OCxN_EN 1 1 1 0 OCxREF Polarity OCx OCxREF xor CCxP OCx_EN 1 Off State output enabled with inactive state OCxN CCxNP OCxN_EN 1 1 1 1 OCREF Polarity dead time OCx_EN 1 Complementary to OCREF not OCREF...

Страница 573: ...nter value 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PSC 15 0 rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw Bits 15 0 PSC 15 0 Prescaler value The counter clock frequency CK_CNT is equal to fCK_PSC PSC...

Страница 574: ...eloaded with REP value only at the repetition update event U_RC any write to the TIMx_RCR register is not taken in account until the next repetition update event It means in PWM mode REP 1 corresponds...

Страница 575: ...active capture compare register contains the value to be compared to the counter TIMx_CNT and signalled on OC2 output If channel CC2 is configured as input CCR2 is the counter value transferred by the...

Страница 576: ...e register contains the value to be compared to the counter TIMx_CNT and signalled on OC4 output If channel CC4 is configured as input CCR4 is the counter value transferred by the last input capture 4...

Страница 577: ...fied as soon as the LOCK level 2 has been programmed LOCK bits in TIMx_BDTR register Bit 10 OSSI Off state selection for Idle mode This bit is used when MOE 0 on channels configured as outputs See OC...

Страница 578: ...ed LOCK bits in TIMx_BDTR register 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved DBL 4 0 Reserved DBA 4 0 rw rw rw rw rw rw rw rw rw rw Bits 15 13 Reserved must be kept at reset value Bits 12 8 DBL 4...

Страница 579: ...IMx 5 Enable the DMA channel Note This example is for the case where every CCRx register to be updated once If every CCRx register is to be updated twice for example the number of data to transfer sho...

Страница 580: ...CC1OF Reserved BIF TIF COMIF CC4IF CC3IF CC2IF CC1IF UIF Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0x14 TIMx_EGR Reserved BG TG COMG CC4G CC3G CC2G CC1G UG Reset value 0 0 0 0 0 0 0 0 0x18 TIMx_CCMR1 Outpu...

Страница 581: ...0 0 0 0 0 0 0 0 0 0 0x3C TIMx_CCR3 Reserved CCR3 15 0 Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0x40 TIMx_CCR4 Reserved CCR4 15 0 Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0x44 TIMx_BDTR Reserved...

Страница 582: ...as described in Section 18 3 15 18 2 TIM2 to TIM5 main features General purpose TIMx timer features include 16 bit TIM3 and TIM4 or 32 bit TIM2 and TIM5 up down up down auto reload counter 16 bit prog...

Страница 583: ...TR1 ITR2 ITR3 TRGI Encoder Interface Capture compare 3 register U CC3I output control OC1 TRGO OC1REF OC2REF OC3REF U UI Reset enable up down count Capture compare 4 register U CC4I OC4REF Prescaler P...

Страница 584: ...in TIMx_CR1 register is set refer also to the slave mode controller description to get more details on counter enabling Note that the actual counter enable signal CNT_EN is set 1 clock cycle after CEN...

Страница 585: ...e counter of the prescaler but the prescale rate does not change In addition if the URS bit update request selection in TIMx_CR1 register is set setting the UG bit generates an update event UEV but wi...

Страница 586: ...k divided by 4 CK_INT 00 CNT_EN Timer clock CK_CNT Counter register Update interrupt flag UIF Counter overflow Update event UEV 01 02 03 04 05 06 07 32 33 34 35 36 31 CK_INT 0035 0000 0001 0002 0003 C...

Страница 587: ...Update event when ARPE 0 TIMx_ARR not preloaded Timer clock CK_CNT Counter register 00 1F 20 Update interrupt flag UIF Counter overflow Update event UEV CK_INT 00 CNT_EN Timer clock CK_CNT Counter re...

Страница 588: ...In addition if the URS bit update request selection in TIMx_CR1 register is set setting the UG bit generates an update event UEV but without setting the UIF flag thus no interrupt or DMA request is s...

Страница 589: ...ivided by 4 CK_INT 36 CNT_EN Timer clock CK_CNT Counter register Update interrupt flag UIF Counter underflow cnt_udf Update event UEV 35 34 33 32 31 30 2F 04 03 02 01 00 05 CK_INT 0001 0036 0035 0034...

Страница 590: ...01 the counter counts up Center aligned mode 2 CMS 10 the counter counts up and down Center aligned mode 3 CMS 11 In this mode the direction bit DIR from TIMx_CR1 register cannot be written It is upd...

Страница 591: ...all the registers are updated and the update flag UIF bit in TIMx_SR register is set depending on the URS bit The buffer of the prescaler is reloaded with the preload value content of the TIMx_PSC reg...

Страница 592: ...low Figure 151 Counter timing diagram internal clock divided by N 0002 0000 0001 0002 0003 CNT_EN TImer clock CK_CNT Counter register Update interrupt flag UIF 0003 0001 Counter underflow Update event...

Страница 593: ...g one timer as prescaler for another timer for example you can configure Timer to act as a prescaler for Timer 2 Refer to Using one timer as prescaler for another timer on page 613 for more details 00...

Страница 594: ...The counter can count at each rising or falling edge on a selected input Figure 155 TI2 external clock connection example For example to configure the upcounter to count in response to a rising edge...

Страница 595: ...edge on TI2 and the actual clock of the counter is due to the resynchronization circuit on TI2 input Figure 156 Control circuit in external clock mode 1 External clock source mode 2 This mode is selec...

Страница 596: ...actual clock of the counter is due to the resynchronization circuit on the ETRP signal Figure 158 Control circuit in external clock mode 2 18 3 4 Capture compare channels Each Capture Compare channel...

Страница 597: ...etector TI1F_Rising TI1F_Falling to the slave mode controller TI1FP1 11 01 TIMx_CCMR1 CC1S 1 0 IC1 TI2FP1 TRC from channel 2 from slave mode controller 10 fDTS TIMx_CCER CC1E IC1PS TI1F TI2F_rising TI...

Страница 598: ...he over capture flag CCxOF TIMx_SR register is set CCxIF can be cleared by software by writing it to 0 or by reading the captured data stored in the TIMx_CCRx register CCxOF is cleared when you write...

Страница 599: ...input capture occurs The TIMx_CCR1 register gets the value of the counter on the active transition CC1IF flag is set interrupt flag CC1OF is also set if at least two consecutive captures occurred wher...

Страница 600: ...onfigure the slave mode controller in reset mode write the SMS bits to 100 in the TIMx_SMCR register Enable the captures write the CC1E and CC2E bits to 1 in the TIMx_CCER register Figure 162 PWM inpu...

Страница 601: ...nds a DMA request if the corresponding enable bit is set CCxDE bit in the TIMx_DIER register CCDS bit in the TIMx_CR2 register for the DMA request selection The TIMx_CCRx registers can be programmed w...

Страница 602: ...y is software programmable using the CCxP bit in the TIMx_CCER register It can be programmed as active high or active low OCx output is enabled by the CCxE bit in the TIMx_CCER register Refer to the T...

Страница 603: ...IMx_CNT TIMx_CCRx else it becomes high If the compare value in TIMx_CCRx is greater than the auto reload value in TIMx_ARR then ocxref is held at 1 0 PWM is not possible in this mode PWM center aligne...

Страница 604: ...s not recommended as it can lead to unexpected results In particular The direction is not updated if you write a value in the counter that is greater than the auto reload value TIMx_CNT TIMx_ARR For e...

Страница 605: ...s different from the counter initial value Before starting when the timer is waiting for the trigger the configuration must be In upcounting CNT CCRx ARR in particular 0 CCRx In downcounting CNT CCRx...

Страница 606: ...Ix input set the CEN bit which enables the counter Then the comparison between the counter and the compare value makes the output toggle But several clock cycles are needed for these operations and it...

Страница 607: ...ions of the two inputs is evaluated and generates count pulses as well as the direction signal Depending on the sequence the counter counts up or down the DIR bit in the TIMx_CR1 register is modified...

Страница 608: ...that the configuration is the following CC1S 01 TIMx_CCMR1 register TI1FP1 mapped on TI1 CC2S 01 TIMx_CCMR2 register TI2FP2 mapped on TI2 CC1P 0 CC1NP 0 IC1F 0000 TIMx_CCER register TI1FP1 noninverted...

Страница 609: ...er input XOR function The TI1S bit in the TIM_CR2 register allows the input filter of channel 1 to be connected to the output of a XOR gate combining the three input pins TIMx_CH1 to TIMx_CH3 The XOR...

Страница 610: ...nding on the level of a selected input In the following example the upcounter counts only when TI1 input is low Configure the channel 1 to detect low levels on TI1 Configure the input filter duration...

Страница 611: ...nd detect low level only Configure the timer in trigger mode by writing SMS 110 in TIMx_SMCR register Select TI2 as the input source by writing TS 110 in TIMx_SMCR register When a rising edge occurs o...

Страница 612: ...register Select TI1 as the input source by writing TS 101 in TIMx_SMCR register A rising edge on TI1 enables the counter and sets the TIF flag The counter then counts on ETR rising edges The delay be...

Страница 613: ..._CR1 register Note If OCx is selected on Timer 1 as trigger output MMS 1xx its rising edge is used to clock the counter of timer 2 Using one timer to enable another timer In this example we control th...

Страница 614: ...2 stops when Timer 1 is disabled by writing 0 to the CEN bit in the TIM1_CR1 register Configure Timer 1 master mode to send its Output Compare 1 Reference OC1REF signal as trigger output MMS 100 in t...

Страница 615: ...th counter clock frequencies are divided by 3 by the prescaler compared to CK_INT fCK_CNT fCK_INT 3 Configure Timer 1 master mode to send its Update Event UEV as trigger output MMS 010 in the TIM1_CR2...

Страница 616: ...R2 register Configure Timer 1 slave mode to get the input trigger from TI1 TS 100 in the TIM1_SMCR register Configure Timer 1 in trigger mode SMS 110 in the TIM1_SMCR register Configure the Timer 1 in...

Страница 617: ...core halted the TIMx counter either continues to work normally or stops depending on DBG_TIMx_STOP configuration bit in DBGMCU module For more details refer to Section 38 16 2 Debug support for timer...

Страница 618: ...r is buffered Bits 6 5 CMS Center aligned mode selection 00 Edge aligned mode The counter counts up or down depending on the direction bit DIR 01 Center aligned mode 1 The counter counts up and down a...

Страница 619: ...abled The Update UEV event is generated by one of the following events Counter overflow underflow Setting the UG bit Update generation through the slave mode controller Buffered registers are then loa...

Страница 620: ...led The Counter Enable signal is generated by a logic OR between CEN control bit and the trigger input when configured in gated mode When the Counter Enable signal is controlled by the trigger input t...

Страница 621: ...this case TS bits must not be 111 3 If external clock mode 1 and external clock mode 2 are enabled at the same time the external clock input is ETRF Bits 13 12 ETPS External trigger prescaler Externa...

Страница 622: ...register and Control Register description 000 Slave mode disabled if CEN 1 then the prescaler is clocked directly by the internal clock 001 Encoder mode 1 Counter counts up down on TI2FP1 edge dependi...

Страница 623: ...ble 0 Trigger DMA request disabled 1 Trigger DMA request enabled Bit 13 Reserved always read as 0 Bit 12 CC4DE Capture Compare 4 DMA request enable 0 CC4 DMA request disabled 1 CC4 DMA request enabled...

Страница 624: ...refer to CC1OF description Bit 11 CC3OF Capture Compare 3 overcapture flag refer to CC1OF description Bit 10 CC2OF Capture compare 2 overcapture flag refer to CC1OF description Bit 9 CC1OF Capture Com...

Страница 625: ...pcounting and up down counting modes or underflow in downcounting mode If channel CC1 is configured as input This bit is set by hardware on a capture It is cleared by software or by reading the TIMx_C...

Страница 626: ...1G Capture compare 1 generation This bit is set by software in order to generate an event it is automatically cleared by hardware 0 No action 1 A capture compare event is generated on channel 1 If cha...

Страница 627: ...FE CC1S 1 0 IC2F 3 0 IC2PSC 1 0 IC1F 3 0 IC1PSC 1 0 rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw Bit 15 OC2CE Output compare 2 clear enable Bits 14 12 OC2M 2 0 Output compare 2 mode Bit 11 OC2PE Ou...

Страница 628: ...can be written at anytime the new value is taken in account immediately 1 Preload register on TIMx_CCR1 enabled Read Write operations access the preload register TIMx_CCR1 preload value is loaded in t...

Страница 629: ...ING fCK_INT N 4 0011 fSAMPLING fCK_INT N 8 0100 fSAMPLING fDTS 2 N 6 0101 fSAMPLING fDTS 2 N 8 0110 fSAMPLING fDTS 4 N 6 0111 fSAMPLING fDTS 4 N 8 1000 fSAMPLING fDTS 8 N 6 1001 fSAMPLING fDTS 8 N 8 1...

Страница 630: ...IC4 is mapped on TI4 10 CC4 channel is configured as input IC4 is mapped on TI3 11 CC4 channel is configured as input IC4 is mapped on TRC This mode is working only if an internal trigger input is sel...

Страница 631: ...re 3 selection This bit field defines the direction of the channel input output as well as the used input 00 CC3 channel is configured as output 01 CC3 channel is configured as input IC3 is mapped on...

Страница 632: ...rising edge Circuit is sensitive to TIxFP1 rising edge capture trigger in reset external clock or trigger mode TIxFP1 is not inverted trigger in gated mode encoder mode 01 inverted falling edge Circui...

Страница 633: ...rw rw rw rw rw rw rw rw rw Bits 15 0 CNT 15 0 Counter value 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PSC 15 0 rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw Bits 15 0 PSC 15 0 Prescaler value The count...

Страница 634: ...ctive capture compare register contains the value to be compared to the counter TIMx_CNT and signaled on OC1 output If channel CC1is configured as input CCR1 is the counter value transferred by the la...

Страница 635: ...register contains the value to be compared to the counter TIMx_CNT and signaled on OC3 output If channel CC3 is configured as input CCR3 is the counter value transferred by the last input capture 3 ev...

Страница 636: ...transfers 10001 18 transfers Bits 7 5 Reserved must be kept at reset value Bits 4 0 DBA 4 0 DMA base address This 5 bit vector defines the base address for DMA transfers when read write access are don...

Страница 637: ...be updated twice for example the number of data to transfer should be 6 Let s take the example of a buffer in the RAM containing data1 data2 data3 data4 data5 and data6 The data is transferred to the...

Страница 638: ...Input 4 remap Set and cleared by software 00 TIM5 Channel4 is connected to the GPIO Refer to the Alternate function mapping table in the datasheets 01 the LSI internal clock is connected to the TIM5_...

Страница 639: ...14 TIMx_EGR Reserved TG Reserved CC4G CC3G CC2G CC1G UG Reset value 0 0 0 0 0 0 0x18 TIMx_CCMR1 Output Compare mode Reserved OC2CE OC2M 2 0 OC2PE OC2FE CC2S 1 0 OC1CE OC1M 2 0 OC1PE OC1FE CC1S 1 0 Res...

Страница 640: ...0 0 0 0 0 0 0 0 0 0 0x3C TIMx_CCR3 CCR3 31 16 TIM2 and TIM5 only reserved on the other timers CCR3 15 0 Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0x40 TIMx_CCR4 CCR4...

Страница 641: ...M14 timers are completely independent and do not share any resources They can be synchronized together as described in Section 19 3 12 19 2 TIM9 to TIM14 main features 19 2 1 TIM9 TIM12 main features...

Страница 642: ...the following events Update counter overflow counter initialization by software Input capture Output compare Auto reload register Capture Compare 1 register Capture Compare 2 register U U U CC1I CC2I...

Страница 643: ...3 14 UTORELOAD REGISTER APTURE OMPARE REGISTER 5 5 3TOP LEAR OUTPUT CONTROL 2 5 5 0RESCALER NPUT FILTER EDGE DETECTOR 03 4 0 2EG EVENT OTES 0RELOAD REGISTERS TRANSFERRED TO ACTIVE REGISTERS ON5 EVENT...

Страница 644: ...TIMx_CR1 register The update event is sent when the counter reaches the overflow and if the UDIS bit equals 0 in the TIMx_CR1 register It can also be generated by software The generation of the updat...

Страница 645: ...CR1 register This is to avoid updating the shadow registers while writing new values in the preload registers Then no update event occurs until the UDIS bit has been written to 0 However the counter r...

Страница 646: ..._ARR The buffer of the prescaler is reloaded with the preload value content of the TIMx_PSC register The following figures show some examples of the counter behavior for different clock frequencies wh...

Страница 647: ...RR not preloaded CK_PSC 0000 0001 CNT_EN Timer clock CK_CNT Counter register Update interrupt flag UIF 0035 0036 Counter overflow Update event UEV Timer clock CK_CNT Counter register 00 1F 20 Update i...

Страница 648: ...k source for TIM10 TIM11 and TIM13 TIM14 For TIM9 and TIM12 the internal clock source is selected when the slave mode controller is disabled SMS 000 The CEN bit in the TIMx_CR1 register and the UG bit...

Страница 649: ...iting CC2P 0 and CC2NP 0 in the TIMx_CCER register 4 Configure the timer in external clock mode 1 by writing SMS 111 in the TIMx_SMCR register 5 Select TI2 as the trigger input source by writing TS 11...

Страница 650: ...nerates a signal TIxFPx which can be used as trigger input by the slave mode controller or as the capture command It is prescaled before the capture register ICxPS Figure 193 Capture compare channel e...

Страница 651: ...of the counter after a transition detected by the corresponding ICx signal When a capture occurs the corresponding CCXIF flag TIMx_SR register is set and an interrupt or a DMA request can be sent if...

Страница 652: ...etected sampled at fDTS frequency Then write IC1F bits to 0011 in the TIMx_CCMR1 register 3 Select the edge of the active transition on the TI1 channel by programming CC1P and CC1NP bits to 00 in the...

Страница 653: ...ure in TIMx_CCR1 and counter clear program the CC1P and CC1NP bits to 00 active on rising edge 3 Select the active input for TIMx_CCR2 write the CC2S bits to 10 in the TIMx_CCMR1 register TI1 selected...

Страница 654: ...ster and the counter the output compare function 1 Assigns the corresponding output pin to a programmable value defined by the output compare mode OCxM bits in the TIMx_CCMRx register and the output p...

Страница 655: ...y setting the OCxPE bit in the TIMx_CCMRx register and eventually the auto reload preload register in upcounting or center aligned modes by setting the ARPE bit in the TIMx_CR1 register As the preload...

Страница 656: ...ous modes It allows the counter to be started in response to a stimulus and to generate a pulse with a programmable length after a programmable delay Starting the counter can be controlled through the...

Страница 657: ...y the difference between the auto reload value and the compare value TIMx_ARR TIMx_CCR1 Let us say you want to build a waveform with a transition from 0 to 1 when a compare match occurs and a transiti...

Страница 658: ...nter is cleared in response to a rising edge on TI1 input 1 Configure the channel 1 to detect rising edges on TI1 Configure the input filter duration in this example we don t need any filter so we kee...

Страница 659: ...as TI1 becomes high The TIF flag in the TIMx_SR register is set both when the counter starts or stops The delay between the rising edge on TI1 and the actual stop of the counter is due to the resynch...

Страница 660: ...synchronization on page 612 for details Note The clock of the slave timer must be enabled prior to receive events from the master timer and must not be changed on the fly while triggers are received f...

Страница 661: ...12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved CKD 1 0 ARPE Reserved OPM URS UDIS CEN rw rw rw rw rw rw rw Bits 15 10 Reserved must be kept at reset value Bits 9 8 CKD Clock division This bit field indicates...

Страница 662: ...DIS Update disable This bit is set and cleared by software to enable disable update event UEV generation 0 UEV enabled An UEV is generated by one of the following events Counter overflow Setting the U...

Страница 663: ...8 7 6 5 4 3 2 1 0 Reserved MSM TS 2 0 Res SMS 2 0 rw rw rw rw rw rw rw Bits 15 8 Reserved must be kept at reset value Bit 7 MSM Master Slave mode 0 No action 1 The effect of an event on the trigger in...

Страница 664: ...en the prescaler is clocked directly by the internal clock 001 Reserved 010 Reserved 011 Reserved 100 Reset mode Rising edge of the selected trigger input TRGI reinitializes the counter and generates...

Страница 665: ...lue Bit 6 TIE Trigger interrupt enable 0 Trigger interrupt disabled 1 Trigger interrupt enabled Bit 5 3 Reserved must be kept at reset value Bit 2 CC2IE Capture Compare 2 interrupt enable 0 CC2 interr...

Страница 666: ...are only when the corresponding channel is configured in input capture mode It is cleared by software by writing it to 0 0 No overcapture has been detected 1 The counter value has been captured in TIM...

Страница 667: ...s been captured in TIMx_CCR1 register an edge has been detected on IC1 which matches the selected polarity Bit 0 UIF Update interrupt flag This bit is set by hardware on an update event It is cleared...

Страница 668: ...CC1IF flag is set the corresponding interrupt is sent if enabled If channel CC1 is configured as input The current counter value is captured in the TIMx_CCR1 register The CC1IF flag is set the corresp...

Страница 669: ...9 8 7 6 5 4 3 2 1 0 Res OC2M 2 0 OC2PE OC2FE CC2S 1 0 Res OC1M 2 0 OC1PE OC1FE CC1S 1 0 IC2F 3 0 IC2PSC 1 0 IC1F 3 0 IC1PSC 1 0 rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw Bit 15 Reserved must be...

Страница 670: ...de Bit 3 OC1PE Output compare 1 preload enable 0 Preload register on TIMx_CCR1 disabled TIMx_CCR1 can be written at anytime the new value is taken into account immediately 1 Preload register on TIMx_C...

Страница 671: ...ING fCK_INT N 4 0011 fSAMPLING fCK_INT N 8 0100 fSAMPLING fDTS 2 N 6 0101 fSAMPLING fDTS 2 N 8 0110 fSAMPLING fDTS 4 N 6 0111 fSAMPLING fDTS 4 N 8 1000 fSAMPLING fDTS 8 N 6 1001 fSAMPLING fDTS 8 N 8 1...

Страница 672: ...ctive high 1 OC1 active low CC1 channel configured as input CC1NP CC1P bits select TI1FP1 and TI2FP1 polarity for trigger or capture operations 00 noninverted rising edge Circuit is sensitive to TIxFP...

Страница 673: ...OCx_EN 1 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 CNT 15 0 rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw Bits 15 0 CNT 15 0 Counter value 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PSC 15 0 rw rw rw rw rw...

Страница 674: ...capture compare register contains the value to be compared to the TIMx_CNT counter and signaled on the OC1 output If channel CC1is configured as input CCR1 is the counter value transferred by the last...

Страница 675: ...F CC1IF UIF Reset value 0 0 0 0 0 0 0x14 TIMx_EGR Reserved TG Reserved CC2G CC1G UG Reset value 0 0 0 0 0x18 TIMx_CCMR1 Output Compare mode Reserved OC2M 2 0 OC2PE OC2FE CC2S 1 0 Reserved OC1M 2 0 OC1...

Страница 676: ...p for the register boundary addresses 0x38 TIMx_CCR2 Reserved CCR2 15 0 Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0x3C to 0x4C Reserved Table 102 TIM9 12 register map and reset values continued Offs...

Страница 677: ...11 Reserved Bit 7 ARPE Auto reload preload enable 0 TIMx_ARR register is not buffered 1 TIMx_ARR register is buffered Bits 6 3 Reserved must be kept at reset value Bit 2 URS Update request source This...

Страница 678: ...enable 0 CC1 interrupt disabled 1 CC1 interrupt enabled Bit 0 UIE Update interrupt enable 0 Update interrupt disabled 1 Update interrupt enabled 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved CC1OF Re...

Страница 679: ...re 0 No update occurred 1 Update interrupt pending This bit is set by hardware when the registers are updated At overflow and if UDIS 0 in the TIMx_CR1 register When CNT is reinitialized by software u...

Страница 680: ...rresponding CCxS bits All the other bits of this register have a different function in input and in output mode For a given bit OCxx describes its function when the channel is configured in output ICx...

Страница 681: ...t compare 1 preload enable 0 Preload register on TIMx_CCR1 disabled TIMx_CCR1 can be written at anytime the new value is taken in account immediately 1 Preload register on TIMx_CCR1 enabled Read Write...

Страница 682: ...fDTS 8 N 8 1010 fSAMPLING fDTS 16 N 5 1011 fSAMPLING fDTS 16 N 6 1100 fSAMPLING fDTS 16 N 8 1101 fSAMPLING fDTS 32 N 5 1110 fSAMPLING fDTS 32 N 6 1111 fSAMPLING fDTS 32 N 8 Bits 3 2 IC1PSC Input capt...

Страница 683: ...e high 1 OC1 active low CC1 channel configured as input The CC1P bit selects TI1FP1 and TI2FP1 polarity for trigger or capture operations 00 noninverted rising edge Circuit is sensitive to TI1FP1 risi...

Страница 684: ...alue 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PSC 15 0 rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw Bits 15 0 PSC 15 0 Prescaler value The counter clock frequency CK_CNT is equal to fCK_PSC PSC 15 0 1...

Страница 685: ...e TIMx_CCMR1 register bit OC1PE Else the preload value is copied in the active capture compare 1 register when an update event occurs The active capture compare register contains the value to be compa...

Страница 686: ...TIMx_SR Reserved CC1OF Reserved CC1IF UIF Reset value 0 0 0 0x14 TIMx_EGR Reserved CC1G UG Reset value 0 0 0x18 TIMx_CCMR1 Output compare mode Reserved OC1M 2 0 OC1PE OC1FE CC1S 1 0 Reset value 0 0 0...

Страница 687: ...imer and must not be changed on the fly while triggers are received from the master timer Refer to Section 2 3 Memory mapfor the register boundary addresses 0x50 TIMx_OR Reserved TI1_RMP Reset value 0...

Страница 688: ...s The timers are completely independent and do not share any resources 20 2 TIM6 TIM7 main features Basic timer TIM6 TIM7 features include 16 bit auto reload upcounter 16 bit programmable prescaler us...

Страница 689: ...g on the auto reload preload enable bit ARPE in the TIMx_CR1 register The update event is sent when the counter reaches the overflow value and if the UDIS bit equals 0 in the TIMx_CR1 register It can...

Страница 690: ...bit in the TIMx_CR1 register This avoids updating the shadow registers while writing new values into the preload registers In this way no update event occurs until the UDIS bit has been written to 0...

Страница 691: ...C register The auto reload shadow register is updated with the preload value TIMx_ARR The following figures show some examples of the counter behavior for different clock frequencies when TIMx_ARR 0x3...

Страница 692: ...loaded 0000 0001 CNT_EN TImer clock CK_CNT Counter register Update interrupt flag UIF 0035 0036 Counter overflow Update event UEV CK_INT Timer clock CK_CNT Counter register 00 1F 20 Update interrupt f...

Страница 693: ...al mode without prescaler Figure 212 Control circuit in normal mode internal clock divided by 1 20 3 4 Debug mode When the microcontroller enters the debug mode Cortex M4 with FPU core halted the TIMx...

Страница 694: ...sources 0 Any of the following events generates an update interrupt or DMA request if enabled These events can be Counter overflow underflow Setting the UG bit Update generation through the slave mode...

Страница 695: ...ime or to control a window in which a slave timer is enabled The Counter Enable signal is generated by a logic OR between CEN control bit and the trigger input when configured in gated mode When the C...

Страница 696: ...ding This bit is set by hardware when the registers are updated At overflow or underflow and if UDIS 0 in the TIMx_CR1 register When CNT is reinitialized by software using the UG bit in the TIMx_EGR r...

Страница 697: ...5 0 Prescaler value The counter clock frequency CK_CNT is equal to fCK_PSC PSC 15 0 1 PSC contains the value to be loaded into the active prescaler register at each update event 15 14 13 12 11 10 9 8...

Страница 698: ...9 8 7 6 5 4 3 2 1 0 0x00 TIMx_CR1 Reserved ARPE Reserved OPM URS UDIS CEN Reset value 0 0 0 0 0 0x04 TIMx_CR2 Reserved MMS 2 0 Reserved Reset value 0 0 0 0x08 Reserved 0x0C TIMx_DIER Reserved UDE Rese...

Страница 699: ...watchdog to react within an accurate timing window For further information on the window watchdog refer to Section 22 on page 704 21 2 IWDG main features Free running downcounter clocked from an inde...

Страница 700: ...or timers watchdog bxCAN and I2C Figure 213 Independent watchdog block diagram Note The watchdog function is implemented in the VDD voltage domain that is still functional in Stop and Standby modes 7...

Страница 701: ...ches 0 Writing the key value 5555h to enable access to the IWDG_PR and IWDG_RLR registers see Section 21 3 2 Writing the key value CCCCh starts the watchdog except if the hardware watchdog option is s...

Страница 702: ...he IWDG_KR register The watchdog counter counts down from this value The timeout period is a function of this value and the clock prescaler Refer to Table 106 The RVU bit in the IWDG_SR register must...

Страница 703: ...boundary addresses Table 107 IWDG register map and reset values Offset Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0x00 IWDG_KR Reserved KEY 15 0 Res...

Страница 704: ...er is refreshed before the downcounter has reached the window register value This implies that the counter must be refreshed in a limited window 22 2 WWDG main features Programmable free running downc...

Страница 705: ...a maximum value due to the unknown status of the prescaler when writing to the WWDG_CR register see Figure 215 The Configuration register WWDG_CFR contains the high limit of the window To prevent a r...

Страница 706: ...terrupt cannot be served e g due to a system lock in a higher priority task the WWDG reset will eventually be generated 22 4 How to program the watchdog timeout You can use the formula in Figure 215 t...

Страница 707: ...s debug mode Cortex M4 with FPU core halted the WWDG counter either continues to work normally or stops depending on DBG_WWDG_STOP configuration bit in DBG module For more details refer to Section 38...

Страница 708: ...7 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved WDGA T 6 0 rs rw Bits 31 8 Reserved must be kept at reset value Bit 7 WDGA Activation bit This bit is set by...

Страница 709: ...set Bits 8 7 WDGTB 1 0 Timer base The time base of the prescaler can be modified as follows 00 CK Counter Clock PCLK1 div 4096 div 1 01 CK Counter Clock PCLK1 div 4096 div 2 10 CK Counter Clock PCLK1...

Страница 710: ...map for the register boundary addresses Table 109 WWDG register map and reset values Offset Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0x00 WWDG_CR...

Страница 711: ...rforms data encryption and decryption using DES and TDES algorithms in Electronic codebook ECB or Cipher block chaining CBC mode The CRYP peripheral is a 32 bit AHB2 peripheral It supports DMA transfe...

Страница 712: ...ck in DES 48 HCLK cycles to process one 64 bit block in TDES Common to DES TDES and AES IN and OUT FIFO each with an 8 word depth a 32 bit width corresponding to 4 DES blocks or 2 AES blocks Automatic...

Страница 713: ...added prior to encryption extra bits should be appended to the trailing end of the data string After decryption the padding has to be discarded The hardware does not manage the padding operation the s...

Страница 714: ...The output is then decrypted using the second key K2 and encrypted using the third key K3 The key depends on the algorithm which is used DES mode Key K1 TDES mode Key K3 K2 K1 where Kx KxR KxL R righ...

Страница 715: ...mode DES TDES ECB mode encryption Figure 218 illustrates the encryption in DES and TDES Electronic codebook DES TDES ECB mode A 64 bit plaintext data block P is used after bit byte half word swapping...

Страница 716: ...O output block P plain text Figure 219 DES TDES ECB mode decryption 1 K key C cipher text I input block O output block P plain text ENCRYPT 0 BITS DECRYPT ENCRYPT 54 PLAINTEXT 0 CIPHERTEXT SWAPPING BI...

Страница 717: ...ues to chain successive cipher and plaintext blocks together until the last plaintext block in the message is encrypted If the message does not consist of an integral number of data blocks then the fi...

Страница 718: ...put block Ps plain text before swapping when decoding or after swapping when encoding P plain text IV initialization vectors ENCRYPT 0 BITS DECRYPT ENCRYPT 54 BITS PLAINTEXT 0 CIPHERTEXT 0S BITS SWAPP...

Страница 719: ...IV The basic processing involved in the AES is as follows an input block of 128 bits is read from the input FIFO and sent to the AEA to be encrypted using the key K0 3 The key format depends on the ke...

Страница 720: ...e encryption To perform an AES decryption in the ECB mode the secret key has to be prepared it is necessary to execute the complete key schedule for encryption by collecting the last round key and usi...

Страница 721: ...ption process continues to chain successive cipher and plaintext blocks together until the last plaintext block in the message is encrypted If the message does not consist of an integral number of dat...

Страница 722: ...CBC mode encryption 1 K key C cipher text I input block O output block Ps plain text before swapping when decoding or after swapping when encoding P plain text IV Initialization vectors 2 IVx IVxR IVx...

Страница 723: ...s each A key K to be used the size does not matter An initial counter block call it ICB but it has the same functionality as the IV of CBC The cipher is computed as follows C i enck iv i xor P i where...

Страница 724: ...ck o output block Ps plain text before swapping when decoding or after swapping when encoding Cs cipher text after swapping when decoding or before swapping when encoding P plain text IV Initializatio...

Страница 725: ...new nonce should be assigned to each different communication The initialization vector IV is a 64 bit value and the standard specifies that the encryptor must choose IV so as to ensure that a given va...

Страница 726: ...he message to be processed is split into 2 parts The header also knows as additional authentication data data which is authenticated but no protected such as information for routing the packet The pay...

Страница 727: ...s started i Write the header data Three methods can be used Program the data by blocks of 32 bits into the CRYP_DIN register and use the IFNF flag to determine if the input FIFO can receive data The s...

Страница 728: ...the corresponding tag An initialization vector is required at the beginning of the algorithm Actually the GMAC algorithm corresponds to the GCM algorithm applied on a message composed of the header on...

Страница 729: ...tor IV e Set the CRYPEN bit to 1 in CRYP_CR f Program the B0 packet into the input data register g Wait for the CRYPEN bit to be cleared before moving on to the next phase h Set CRYPEN to 1 2 CCM head...

Страница 730: ...the authentication tag of the message is generated and stored in the CRYP_DOUT register p Configure GCM_CCMPH 1 0 bits to 11 in CRYP_CR q Load the A0 initialized counter and program the 128 bit A0 va...

Страница 731: ...register CRYP_CR Figure 229 shows how the 64 bit data block M1 64 is constructed from two consecutive 32 bit words popped off the IN FIFO by the CRYP processor according to the DATATYPE value The sam...

Страница 732: ...YTE YTE BITS BITS BITS BITS BIT STRING HALD WORD SWAPPING OPERATION ALF WORD BITS 4 490 B 4 490 B 4 490 B ALF WORD BITS ALF WORD ALF WORD BIT BIT BIT BIT BIT BIT BIT BIT BIT BIT FIRST WORD WRITTEN IN...

Страница 733: ...of the IN FIFO then the IN FIFO is popped and a new 64 bit data block can be processed During the AES CBC encryption the CRYP_IV0 1 L R bits are XORed with the 128 bit data block popped off the IN FIF...

Страница 734: ...S algorithm 16 AHB2 clock cycles for the simple DES algorithm and 14 16 or 18 AHB2 clock cycles for the AES with key lengths of 128 192 or 256 bits respectively During the whole process the BUSY bit i...

Страница 735: ...before preparing the key and the algorithm must be configured once the key has been prepared a Configure the key size 128 192 or 256 bit in the AES only with the KEYSIZE bits in the CRYP_CR register b...

Страница 736: ...ered into the FIFO disable the interrupt by clearing the INIM bit 4 In the interrupt managing the output data read the output message from the OUT FIFO You can read 1 block 2 or 4 words at a time or r...

Страница 737: ...35 Initialization with the saved configuration For the AES ECB or AES CBC decryption the key must be prepared again b If needed reconfigure the DMA controller to transfer the rest of the message c Ena...

Страница 738: ...ted if any of the individual interrupts listed below is asserted and enabled You can enable or disable the interrupt sources individually by changing the mask bits in the CRYP_IMSCR register Setting t...

Страница 739: ...signal is deasserted a request signal can become active again depending on the above described conditions All request signals are deasserted if the CRYP peripheral is disabled or the DMA enable bit is...

Страница 740: ...th of the key used for the AES cryptographic core This bitfield is don t care in the DES or TDES modes 00 128 bit key length 01 192 bit key length 10 256 bit key length 11 Reserved do not use this val...

Страница 741: ...rithm Initialization vectors CRYP_IV0L R must be initialized Only one key vector K1 is used K0 K2 K3 are not used 100 AES ECB AES Electronic codebook no feedback between blocks of data Initialization...

Страница 742: ...0 or 1 has no effect Reading this bit always returns 0 Bits 13 10 Reserved forced by hardware to 0 Bits 9 8 KEYSIZE 1 0 Key size selection AES mode only This bitfield defines the bit length of the ke...

Страница 743: ...AES Electronic codebook no feedback between blocks of data Initialization vectors CRYP_IV0L R 1L R are not used All four key vectors K0 K3 are used 0101 AES CBC AES Cipher block chaining output block...

Страница 744: ...YPEN 0 in the CRYP_CR register and the last processing has completed or The CRYP core is waiting for enough data in the input FIFO or enough free space in the output FIFO that is in each case at least...

Страница 745: ...in the CRYP_CR register Refer to Section 23 3 3 Data type on page 730 for more details When CRYP_DIN register is written to the data are pushed into the input FIFO When at least two 32 bit words in t...

Страница 746: ...31 of the first word read from the FIFO bit 64 rightmost bit corresponds to the LSB bit 0 of the second word read from the FIFO In the AES mode Bit 0 leftmost bit corresponds to the MSB bit 31 of the...

Страница 747: ...t 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved DOEN DIEN rw rw Bits 31 2 Reserved must be kept at reset value Bit 1 DOEN DMA output enable 0...

Страница 748: ...egister gives the current masked status of the corresponding interrupt prior to masking A write has no effect 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2...

Страница 749: ...o b255 b0 In any case b0 is the rightmost bit CRYP_K0LR address offset 0x20 CRYP_K0RR address offset 0x24 Bits 31 2 Reserved must be kept at reset value Bit 1 OUTMIS Output FIFO service masked interru...

Страница 750: ...29 28 27 26 25 24 23 22 21 20 19 18 17 16 k2 1 b127 k2 2 b126 k2 3 b125 k2 4 b124 k2 5 b123 k2 6 b122 k2 7 b121 k2 8 b120 k2 9 b119 k2 10 b118 k2 11 b117 k2 12 b116 k2 13 b115 k2 14 b114 k2 15 b113 k...

Страница 751: ...P_IV0LR address offset 0x40 CRYP_IV0RR address offset 0x44 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 k3 33 b31 k3 34 b30 k3 35 b29 k3 36 b28 k3 37 b27 k3 38 b26 k3 39 b25 k3 40 b24 k3 41 b23 k3...

Страница 752: ...5 IV76 IV77 IV78 IV79 rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 IV80 IV81 IV82 IV83 IV84 IV85 IV86 IV87 IV88 IV89 IV90 IV91 IV92 IV93 IV94 IV95 rw rw rw rw...

Страница 753: ...C mode or CRYP_CSGCMCCM0 7R in CCM CMAC mode registers have to be read and the values retrieved have to be saved in the system memory space The cryptographic processor can then be used by the preempti...

Страница 754: ...set value 0 0 0 0 0 0 0 0 0 0 0 0 0 0x10 CRYP_DMAC R Reserved DOEN DIEN Reset value 0 0 0x14 CRYP_IMSC R Reserved OUTIM INIM Reset value 0 0 0x18 CRYP_RISR Reserved OUTRIS INRIS Reset value 0 1 0x1C C...

Страница 755: ...18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Table 114 CRYP register map and reset values for STM32F43xxx Offset Register name reset value 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 1...

Страница 756: ...0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0x48 CRYP_IV1LR CRYP_IV1LR Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0x4C CRYP_IV1RR CRYP_IV1RR Reset value 0 0 0 0 0 0 0 0 0 0 0...

Страница 757: ..._CSGCM1R Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0x78 CRYP_CSGC M2R CRYP_CSGCM2R Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0x7C CR...

Страница 758: ...the RNG entropy to flag abnormal behavior generation of stable values or of a stable sequence of values It can be disabled to reduce power consumption 24 3 RNG functional description Figure 232 shows...

Страница 759: ...DY bit is 1 in the RNG_SR register The contents of the RNG_DR register can then be read As required by the FIPS PUB Federal Information Processing Standard Publication 140 2 the first random number ge...

Страница 760: ...at reset value 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved SEIS CEIS Reserved SECS CECS DRDY rc_w0 rc_w0 r r r Bits 31 3 Reserved must be k...

Страница 761: ...ted More than 64 consecutive bits at the same value 0 or 1 More than 32 consecutive alternances of 0 and 1 0101010101 01 Bit 1 CECS Clock error current status 0 The RNG_CLK clock has been correctly de...

Страница 762: ...et values Table 115 RNG register map and reset map Offset Register name reset value Register size 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0x00 RNG_CR 0x00...

Страница 763: ...D5 SHA 224 and SHA 256 are available on STM32F43xxx only AHB slave peripheral 32 bit data words for input data supporting word half word byte and bit bit string representations with little endian data...

Страница 764: ...ure 233 Block diagram for STM32F415 417xx BIT BUS ASH 3 3 SWA PPIN G BIT 3 2 3 3 32 CONTEXT DIGEST 3 2 3 32 NTERRUPT REGISTERS ONTROL REGISTER ONTEXT SWAPPING ESSAGE DIGEST PROCESSOR CORE 3 34 2 3TART...

Страница 765: ...MD5 are qualified as secure because it is computationally infeasible to find a message that corresponds to a given message digest or to find two different messages that produce the same message digest...

Страница 766: ...time needed to process the last block of a message or of a key in HMAC can be longer This time depends on the length of the last block and the size of the key in HMAC mode Compared to the processing o...

Страница 767: ...T S 3 A L F W O R D S W A PPING O P ER A T IO N B I T STR IN G G R O WS I N T H IS D I RECT I O N A S D E FI N E D B Y 03 05 S T D ALF WO R D BI T S 4 490 BX 4 4 90 BX 4 4 90 BX ALF WO R D BI T S ALF...

Страница 768: ...t block entered this is done by writing the DCAL bit to 1 When the DMA is used The contents of the HASH_DIN register are interpreted automatically with the information sent by the DMA controller In ca...

Страница 769: ...d with the value 24 a 1 is appended at bit location 24 in the bit string starting counting from left to right in the above bit string which corresponds to bit 31 in the HASH_DIN register little endian...

Страница 770: ...message If DMA transfers are used refer to the Procedure where the data are loaded by DMA section Otherwise if the message length is not an exact multiple of 512 bits then the HASH_STR register has t...

Страница 771: ...ion 4 After the first hash round the hash processor returns ready to indicate that it is ready to receive the key to be used for the outer hash function normally this key is the same as the one used f...

Страница 772: ...redict if a DMA transfer is in progress or if the process is ongoing Thus you must stop the DMA transfers then wait until the HASH is ready in order to interrupt the processing of a message Interrupti...

Страница 773: ...ve message digest registers All these registers are accessible through word accesses only else an AHB error is generated 25 4 1 HASH control register HASH_CR for STM32F415 417xx Address offset 0x00 Re...

Страница 774: ...nto the DIN buffer If the DMA is used NBW is the exact number of words that have been pushed into the IN FIFO Bit 7 ALGO 1 0 Algorithm selection These bits selects the SHA 1 or the MD5 algorithm 0 SHA...

Страница 775: ...n the INIT bit is written to 1 2 If this bit is written to 0 while a DMA transfer has already been requested to the DMA DMAE is cleared but the current transfer is not aborted Instead the DMA interfac...

Страница 776: ...key 64 bytes Note This selection is only taken into account when the INIT bit is set and MODE 1 Changing this bit during a computation has no effect Bits 15 14 Reserved forced by hardware to 0 Bit 13...

Страница 777: ...0 SHA 1 algorithm selected 01 MD5 algorithm selected 10 SHA224 algorithm selected 11 SHA256 algorithm selected Note This selection is only taken into account when the INIT bit is set Changing this bit...

Страница 778: ...the INIT bit is written to 1 2 If this bit is written to 0 while a DMA transfer has already been requested to the DMA DMAE is cleared but the current transfer is not aborted Instead the DMA interface...

Страница 779: ...tion automatically if the DMA is used When the last block has been written to the HASH_DIN register the final digest calculation including padding is launched by writing the DCAL bit to 1 in the HASH_...

Страница 780: ...Bits 7 5 Reserved forced by hardware to 0 Bits 4 0 NBLW Number of valid bits in the last word of the message in the bit string organization of hash processor When these bits are written and DCAL is a...

Страница 781: ...as zero 4 H0 to H7 respectively in the SHA256 algorithm description If a read access to one of these registers occurs while the HASH core is calculating an intermediate digest or a final message dige...

Страница 782: ...r r r r r r r r r 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 H3 r r r r r r r r r r r r r r r r 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 H4 r r r r r r r r r r r r r r r r 15 14 13 12 11 10 9 8 7 6...

Страница 783: ...r r r r r r r r r r r r r r r r 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 H7 r r r r r r r r r r r r r r r r 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0...

Страница 784: ...1 DMA interface is enabled DMAE 1 or a transfer is ongoing Bit 1 DCIS Digest calculation completion interrupt status This bit is set by hardware when a digest becomes ready the whole message has been...

Страница 785: ...to be done because a high priority task has to use the hash processor while it is already in use by another task When such an event occurs the HASH_CSRx registers have to be read and the read values...

Страница 786: ...0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0x10 HASH_HR1 H1 Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0x14 HASH_HR2 H2 Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0...

Страница 787: ...DE DATATYPE DMAE INIT Reserved Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0x04 HASH_DIN DATAIN Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0x08 HASH_STR Reserved DCAL Rese...

Страница 788: ...0 0 0 0 0 0 0 0 0 0 0 0 0 0x318 HASH_HR2 H2 Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0x31 C HASH_HR3 H3 Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0...

Страница 789: ...week date day of month month and year expressed in binary coded decimal format BCD The sub seconds value is also available in binary format Compensations for 28 29 leap year 30 and 31 day months are...

Страница 790: ...ppm accuracy obtained in a calibration window of several seconds Timestamp function for event saving 1 event Tamper detection 2 tamper events with configurable filter and internal pull up 20 backup re...

Страница 791: ...t asynchronous prescaler configured through the PREDIV_A bits of the RTC_PRER register A 15 bit synchronous prescaler configured through the PREDIV_S bits of the RTC_PRER register Note When both presc...

Страница 792: ...o RTCCLK periods the current calendar value is copied into the shadow registers and the RSF bit of RTC_ISR register is set see Section 26 6 4 The copy is not performed in Stop and Standby mode When ex...

Страница 793: ...rupt period from 122 s to 32 s with a resolution down to 61 s ck_spre usually 1 Hz internal clock When ck_spre frequency is 1Hz this allows to achieve a wakeup time from 1 s to around 36 hours with on...

Страница 794: ...to 1 in the RTC_ISR register to enter initialization mode In this mode the calendar counter is stopped and its value can be updated 2 Poll INITF bit of in the RTC_ISR register The initialization phas...

Страница 795: ...ar WUTE in RTC_CR to disable the wakeup timer 2 Poll WUTWF until it is set in RTC_ISR to make sure the access to wakeup auto reload counter and to WUCKSEL 2 0 bits is allowed It takes 1 to 2 RTCCLK cl...

Страница 796: ...counters directly thus eliminating the need to wait for the RSF bit to be set This is especially useful after exiting from low power modes STOP or Standby since the shadow registers are not updated d...

Страница 797: ...ith a resolution of 1 PREDIV_S 1 seconds The shift operation consists of adding the SUBFS 14 0 value to the synchronous prescaler counter SS 15 0 this will delay the clock If at the same time the ADD1...

Страница 798: ...C coarse digital calibration Two digital calibration methods are available coarse and smooth calibration To perform coarse calibration refer to Section 26 6 7 RTC calibration register RTC_CALIBR The t...

Страница 799: ...a 512 Hz clock is output for calibration Refer to Section 26 3 14 Calibration clock output 26 3 11 RTC smooth digital calibration RTC frequency can be digitally calibrated with a resolution of about 0...

Страница 800: ...d so that each second is accelerated by 8 RTCCLK clock cycles which is equivalent to adding 256 clock cycles every 32 seconds As a result between 255 and 256 clock pulses corresponding to a calibratio...

Страница 801: ...RTC_CALR can be updated on the fly while RTC_ISR INITF 0 by using the follow process 1 Poll the RTC_ISR RECALPF re calibration pending flag 2 If it is set to 0 write a new value to RTC_CALR if necessa...

Страница 802: ...y are implemented in the backup domain that remains powered on by VBAT when the VDD power is switched off They are not reset by system reset or when the device wakes up from Standby mode They are rese...

Страница 803: ...tamper inputs Level detection with filtering is performed by setting TAMPFLT to a non zero value A tamper detection event is generated when either 2 4 or 8 depending on TAMPFLT consecutive samples are...

Страница 804: ...The OSEL 1 0 control bits in the RTC_CR register are used to activate the alarm alternate function output RTC_ALARM in RTC_AF1 and to select the function which is output on RTC_ALARM The polarity of t...

Страница 805: ...XTI Line 21 in interrupt mode and select the rising edge sensitivity 2 Configure and Enable the TAMP_STAMP IRQ channel in the NVIC 3 Configure the RTC to detect the RTC tamper event To enable the RTC...

Страница 806: ...HAD 1 Note This register is write protected The write access procedure is described in RTC register write protection on page 794 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved PM HT 1 0 HU 3...

Страница 807: ...e access procedure is described in RTC register write protection on page 794 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved YT 3 0 YU 3 0 rw rw rw rw rw rw rw rw 15 14 13 12 11 10 9 8 7 6 5...

Страница 808: ...ed Bit 20 POL Output polarity This bit is used to configure the polarity of RTC_ALARM output 0 The pin is high when ALRAF ALRBF WUTF is asserted depending on OSEL 1 0 1 The pin is low when ALRAF ALRBF...

Страница 809: ...enabled Bit 11 TSE Time stamp enable 0 Time stamp disable 1 Time stamp enable Bit 10 WUTE Wakeup timer enable 0 Wakeup timer disabled 1 Wakeup timer enabled Bit 9 ALRBE Alarm B enable 0 Alarm B disab...

Страница 810: ...pt INIT INITF and RSF which are cleared to 0 Bit 4 REFCKON Reference clock detection enable 50 or 60 Hz 0 Reference clock detection disabled 1 Reference clock detection enabled Note PREDIV_S must be 0...

Страница 811: ...ediately before the TSF bit is cleared Bit 11 TSF Timestamp flag This flag is set by hardware when a timestamp event occurs This flag is cleared by software by writing 0 Bit 10 WUTF Wakeup timer flag...

Страница 812: ...Shift operation pending 0 No shift operation is pending 1 A shift operation is pending This flag is set by hardware as soon as a shift operation is initiated by a write to the RTC_SHIFTR It is cleared...

Страница 813: ...value 0x0000 FFFF System reset not affected 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved PREDIV_A 6 0 rw rw rw rw rw rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res PREDIV_S 14 0 rw rw rw...

Страница 814: ...gnificant bit to be reloaded into the timer Note The first assertion of WUTF occurs WUT 1 ck_wut cycles after WUTE is set Setting WUT 15 0 to 0x0000 with WUCKSEL 2 0 011 RTCCLK 2 is forbidden 31 30 29...

Страница 815: ...ay match 1 Date day don t care in Alarm A comparison Bit 30 WDSEL Week day selection 0 DU 3 0 represents the date units 1 DU 3 0 represents the week day DT 1 0 is don t care Bits 29 28 DT 1 0 Date ten...

Страница 816: ...ate and day match 1 Date and day don t care in Alarm B comparison Bit 30 WDSEL Week day selection 0 DU 3 0 represents the date units 1 DU 3 0 represents the week day DT 1 0 is don t care Bits 29 28 DT...

Страница 817: ...7 6 5 4 3 2 1 0 Reserved KEY w w w w w w w w Bits 31 8 Reserved must be kept at reset value Bits 7 0 KEY Write protection key This byte is written by software Reading this byte always returns 0x00 Ref...

Страница 818: ...tended to be used with SUBFS see description below in order to effectively add a fraction of a second to the clock in an atomic operation Bits 30 15 Reserved Bits 14 0 SUBFS Subtract a fraction of a s...

Страница 819: ...ur format 1 PM Bits 21 20 HT 1 0 Hour tens in BCD format Bits 19 16 HU 3 0 Hour units in BCD format Bit 15 Reserved must be kept at reset value Bits 14 12 MNT 2 0 Minute tens in BCD format Bits 11 8 M...

Страница 820: ...up domain reset value 0x0000 0000 System reset not affected 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved r r r r r r r r r r r r r r r r 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 SS 15 0 r r r...

Страница 821: ...CALW8 Use an 8 second calibration cycle period When CALW8 is set to 1 the 8 second calibration cycle period is selected CALM 1 0 are stuck at 00 when CALW8 1 Refer to Section 26 3 11 RTC smooth digita...

Страница 822: ...in output 1 RTC_ALARM is a push pull output Bit 17 TSINSEL TIMESTAMP mapping 0 RTC_AF1 used as TIMESTAMP 1 RTC_AF2 used as TIMESTAMP Bit 16 TAMP1INSEL TAMPER1 mapping 0 RTC_AF1 used as TAMPER1 1 RTC_A...

Страница 823: ...32768 Hz 0x2 RTCCLK 8192 4 Hz when RTCCLK 32768 Hz 0x3 RTCCLK 4096 8 Hz when RTCCLK 32768 Hz 0x4 RTCCLK 2048 16 Hz when RTCCLK 32768 Hz 0x5 RTCCLK 1024 32 Hz when RTCCLK 32768 Hz 0x6 RTCCLK 512 64 Hz...

Страница 824: ...w rw rw rw w rw rw Bits 31 28 Reserved Bits 27 24 MASKSS 3 0 Mask the most significant bits starting at this bit 0 No comparison on sub seconds for Alarm A The alarm is set when the seconds unit is in...

Страница 825: ...rved Bits 27 24 MASKSS 3 0 Mask the most significant bits starting at this bit 0x0 No comparison on sub seconds for Alarm B The alarm is set when the seconds unit is incremented assuming that the rest...

Страница 826: ...es Offset Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0x00 RTC_TR Reserved PM HT 1 0 HU 3 0 Reserved MNT 2 0 MNU 3 0 Reserved ST 2 0 SU 3 0 Reset val...

Страница 827: ...0 0 0 0 0 0 0x38 RTC_TSSSR Reserved SS 15 0 Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0x3C RTC_ CALR Reserved CALP CALW8 CALW16 Reserved CALM 8 0 Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0x40 RTC_TAFCR R...

Страница 828: ...ction Memory map for the register boundary addresses Caution In Table 120 the reset value is the value after a backup domain reset The majority of the registers are not affected by a system reset For...

Страница 829: ...can be available for reduced CPU overload 27 2 I2C main features Parallel bus I2C protocol converter Multimaster capability the same interface can act as Master or Slave I2C Master features Clock gene...

Страница 830: ...terface converts it from serial to parallel format and vice versa The interrupts are enabled or disabled by software The interface is connected to the I2C bus by a data pin SDA and by a clock pin SCL...

Страница 831: ...aster mode A 9th clock pulse follows the 8 clock cycles of a byte transfer during which the receiver must send an acknowledge bit to the transmitter Refer to Figure 238 Figure 238 I2 C bus protocol Ac...

Страница 832: ...gram for STM32F40x 41x Data shift register Comparator Own address register Clock control Status registers Control registers Control Clock control Data control SCL logic Dual address register Data regi...

Страница 833: ...ock frequency must be at least 2 MHz in Sm mode 4 MHz in Fm mode As soon as a start condition is detected the address is received from the SDA line and sent to the shift register Then it is compared w...

Страница 834: ...e on receiving a repeated Start condition followed by the header sequence with matching address bits and the least significant bit set 11110xx1 The TRA bit indicates whether the slave is in Receiver o...

Страница 835: ...if the ITEVFEN and ITBUFEN bit is set If RxNE is set and the data in the DR register is not read before the end of the next data reception the BTF bit is set and the interface waits until BTF is clea...

Страница 836: ...ee Figure 242 Transfer sequence diagram for slave receiver EV4 27 3 3 I2 C master mode In Master mode the I2 C interface initiates a data transfer and generates the clock signal A serial data transfer...

Страница 837: ...te a Start condition and to switch to Master mode MSL bit set when the BUSY bit is cleared Note In master mode setting the START bit causes the interface to generate a ReStart condition at the end of...

Страница 838: ...s in Receiver or Transmitter mode Master transmitter Following the address transmission and after clearing ADDR the master sends bytes from the DR register to the SDA line via the internal shift regis...

Страница 839: ...e EVx Event with interrupt if ITEVFEN 1 EV5 SB 1 cleared by reading SR1 register followed by writing DR register with Address EV6 ADDR 1 cleared by reading SR1 register followed by reading SR2 EV8_1 T...

Страница 840: ...s until BTF is cleared by a read in the DR register stretching SCL low Closing the communication The master sends a NACK for the last byte received from the slave After receiving this NACK the slave r...

Страница 841: ...without reception of supplementary data For 2 byte reception Wait until ADDR 1 SCL stretched low until the ADDR flag is cleared Set ACK low set POS high Clear ADDR flag Wait until BTF 1 Data 1 in DR D...

Страница 842: ...placed Stop the slave behaves like for a Stop condition and the lines are released by hardware In Master mode the lines are not released and the state of the current transmission is not affected It is...

Страница 843: ...ore the first SCL rising edge If not possible the receiver must discard the first data 27 3 5 Programmable noise filter The programmable noise filter is available on STM32F42xxx and STM32F43xxx device...

Страница 844: ...n Write Collision not managed 27 3 7 SMBus Introduction The System Management Bus SMBus is a two wire interface through which various devices can communicate with each other and with the rest of the s...

Страница 845: ...ddress resolution protocol ARP SMBus slave address conflicts can be resolved by dynamically assigning a new unique address to each slave device The Address Resolution Protocol ARP has the following at...

Страница 846: ...ng the slave address the device must disengage its SMBA pull down If the host still sees SMBA low when the message transfer is complete it knows to read the ARA again A host which does not implement t...

Страница 847: ...programmed during EV6 event i e program ACK 0 when ADDR 1 before clearing ADDR flag Then the user can program the STOP condition either after clearing ADDR flag or in the DMA Transfer Complete interru...

Страница 848: ...ansfer depending on application requirements 6 Activate the stream by setting the EN bit in the DMA_SxCR register When the number of data transfers which has been programmed in the DMA Controller regi...

Страница 849: ...f it is really the last DMA transfer or not If it is the last DMA request for a master receiver a NACK is automatically sent after the last received byte PEC calculation is corrupted by an arbitration...

Страница 850: ...circuit I2C interface RM0090 850 1731 DocID018909 Rev 11 Figure 245 I2 C interrupt mapping diagram ADDR SB ADD10 RxNE TxE BTF it_event ARLO BERR AF OVR PECERR TIMEOUT SMBALERT ITERREN it_error ITEVFE...

Страница 851: ...w rw rw rw rw rw rw rw rw rw rw rw rw rw Bit 15 SWRST Software reset When set the I2C is under reset state Before resetting this bit make sure the I2C lines are released and the bus is free 0 I2 C Per...

Страница 852: ...re cleared by hardware when a Stop condition is detected set by hardware when a timeout error is detected In Master Mode 0 No Stop generation 1 Stop generation after the current byte transfer or after...

Страница 853: ...communication when back to IDLE state All bit resets due to PE 0 occur at the end of the communication In master mode this bit must not be reset before the end of the communication 15 14 13 12 11 10 9...

Страница 854: ...s generated when BERR 1 ARLO 1 AF 1 OVR 1 PECERR 1 TIMEOUT 1 SMBALERT 1 Bits 7 6 Reserved must be kept at reset value Bits 5 0 FREQ 5 0 Peripheral clock frequency The FREQ bits must be configured with...

Страница 855: ...d always be kept at 1 by software Bits 13 10 Reserved must be kept at reset value Bits 9 8 ADD 9 8 Interface address 7 bit addressing mode don t care 10 bit addressing mode bits9 8 of address Bits 7 1...

Страница 856: ...ten in the DR register A continuous transmit stream can be maintained if the next data to be transmitted is put in DR once the transmission is started TxE 1 Receiver mode Received byte is copied into...

Страница 857: ...r receiver returns ACK after PEC reception if ACK 1 1 PEC error receiver returns NACK after PEC reception whatever ACK Cleared by software writing 0 or by hardware when PE 0 Note When the received CRC...

Страница 858: ...e after a start or a stop condition or when PE 0 TxE is not set if either a NACK is received or if next byte to be transmitted is PEC PEC 1 Note TxE is not cleared by writing the first data being tran...

Страница 859: ...is the PEC TRA 1 in I2C_SR2 register and PEC 1 in I2C_CR1 register Bit 1 ADDR Address sent master mode matched slave mode This bit is cleared by software reading SR1 register followed reading SR2 or...

Страница 860: ...ode 0 Received address matched with OAR1 1 Received address matched with OAR2 Cleared by hardware after a Stop condition or repeated Start condition or when PE 0 Bit 6 SMBHOST SMBus host header Slave...

Страница 861: ...bit is set depending on the R W bit of the address byte at the end of total address phase It is also cleared by hardware after detection of Stop condition STOPF 1 repeated Start condition loss of bus...

Страница 862: ...ns of parameters I2C communication speed fSCL 1 thigh tlow The real frequency may differ due to the analog noise filter input delay The CCR register must be configured only when the I2 C is disabled P...

Страница 863: ...filter disable Note ANOFF must be configured only when the I2C is disabled PE 0 Bits 3 0 DNF 3 0 Digital noise filter These bits are used to configure the digital noise filter on SDA and SCL inputs T...

Страница 864: ...EN ITEVTEN ITERREN Reserved FREQ 5 0 Reset value 0 0 0 0 0 0 0 0 0 0 0 0x08 I2C_OAR1 Reserved ADDMODE Reserved ADD 9 8 ADD 7 1 ADD0 Reset value 0 0 0 0 0 0 0 0 0 0 0 0x0C I2C_OAR2 Reserved ADD2 7 1 EN...

Страница 865: ...e bidirectional data line or reliable communication using CRC checking The I2 S is also a synchronous serial communication interface It can address four different audio standards including the I2 S Ph...

Страница 866: ...ion for both master and slave NSS management by hardware or software for both master and slave dynamic change of master slave operations Programmable clock polarity and phase Programmable data order w...

Страница 867: ...lag in reception and transmission mode slave only 16 bit register for transmission and reception with one data register for both channel sides Supported I2S protocols I2S Phillps standard MSB justifie...

Страница 868: ...he SPI master communicate with slaves individually and to avoid contention on the data lines Slave NSS inputs can be driven by standard IO ports on the master device The NSS pin may also be used as an...

Страница 869: ...Software NSS management SSM 1 The slave select information is driven internally by the value of the SSI bit in the SPI_CR1 register The external NSS pin remains free for other application uses Hardwar...

Страница 870: ...ed on the occurrence of the first clock transition The combination of the CPOL clock polarity and CPHA clock phase bits selects the data capture clock edge Figure 248 shows an SPI transfer with the fo...

Страница 871: ...SCK pin from the master device The value set in the BR 2 0 bits in the SPI_CR1 register does not affect the data transfer rate Note It is recommended to enable the SPI slave before the master sends th...

Страница 872: ...buffer during a write cycle The transmit sequence begins when the slave device receives the clock signal and the most significant bit of the data on its MOSI pin The remaining bits the 7 bits in 8 bit...

Страница 873: ...orola SPI communications FRF bit set to 0 To detect TI frame errors in Slave transmitter only mode by using the Error interrupt ERRIE 1 the SPI must be configured in 2 line unidirectional mode by sett...

Страница 874: ...and the MISO pin is a data input Transmit sequence The transmit sequence begins when a byte is written in the Tx Buffer The data byte is parallel loaded into the shift register from the internal bus...

Страница 875: ...makes the configuration of NSS management through the SPI_CR1 and SPI_CR2 registers SSM SSI SSOE transparent for the user Figure 251 TI mode master mode single transfer and Figure 252 TI mode master...

Страница 876: ...n be used as a general purpose IO In this case the application just needs to ignore the Rx buffer if the data register is read it does not contain the received value In receive only mode the applicati...

Страница 877: ...d BIDIOE 0 The received data on the MOSI pin are shifted in serially to the 8 bit shift register and then parallel loaded into the SPI_DR register Rx buffer The transmitter is not activated and no dat...

Страница 878: ...fer The RXNE flag Rx buffer not empty is set on the last sampling clock edge when the data are transferred from the shift register to the Rx buffer It indicates that data are ready to be read from the...

Страница 879: ...2 from SPI_ DR software waits until RXNE 1 and reads 0xA3 from SPI_DR b0 b1 b2 b3 b4 b5 b6 b7 b0 b1 b2 b3 b4 b5 b6 b7 b0 b1 b2 b3 b4 b5 b6 b7 b0 b1 b2 b3 b4 b5 b6 b7 b0 b1 b2 b3 b4 b5 b6 b7 b0 b1 b2 b...

Страница 880: ...ions there is a 2 APB clock period delay between the write operation to SPI_DR and the BSY bit setting As a consequence in transmit only mode it is mandatory to wait first until TXE is set and then un...

Страница 881: ...aster device drives NSS low and generates the SCK clock 3 Wait until RXNE 1 and read the SPI_DR register to get the received data this clears the RXNE bit Repeat this operation for each data item to b...

Страница 882: ...BSY bit is never cleared between each data transfer On the contrary if the software is not fast enough this can lead to some discontinuities in the communication In this case the BSY bit is cleared be...

Страница 883: ...to be transferred is written to the SPI_DR At the end of this last data transfer the SPI_TXCRCR value is transmitted In receive only mode and when the transfers are managed by software CPU mode it is...

Страница 884: ...le CRC calculation only when the clock is stable that is when the clock is in the steady state If not a wrong CRC calculation may be done In fact the CRC is sensitive to the SCK slave input clock as s...

Страница 885: ...re the BSY flag is kept low during reception The BSY flag is useful to detect the end of a transfer if the software wants to disable the SPI and enter Halt mode or disable the peripheral clock This av...

Страница 886: ...1 2 Then wait until BSY 0 3 Disable the SPI SPE 0 and eventually enter the Halt mode or disable the peripheral clock In master unidirectional receive only mode MSTR 1 BIDIMODE 0 RXONLY 1 or bidirectio...

Страница 887: ...In transmission a DMA request is issued each time TXE is set to 1 The DMA then writes to the SPI_DR register this clears the TXE flag In reception a DMA request is issued each time RXNE is set to 1 T...

Страница 888: ...into SPI_DR DMA writes DATA3 into SPI_DR software waits until BSY 0 DMA transfer complete DMA transfer is complete TCIF 1 in DMA_ISR software waits until TXE 1 DMA transfer is complete b0 b1 b2 b3 b4...

Страница 889: ...te to the SPI_CR1 register To avoid any multiple slave conflicts in a system comprising several MCUs the NSS pin must be pulled high during the MODF bit clearing sequence The SPE and MSTR bits can be...

Страница 890: ...nsfer The data may be corrupted since the error detection may result in the lost of two data bytes The FRE flag is cleared when SPI_SR register is read If the bit ERRIE is set an interrupt is generate...

Страница 891: ...e The SPI could function as an audio I2S interface when the I2S capability is enabled by setting the I2SMOD bit in the SPI_I2SCFGR register This interface uses almost the same pins flags and interrupt...

Страница 892: ...s its own clock generator to produce the communication clock when it is set in master mode This clock generator is also the source of the master clock output Two additional registers are available in...

Страница 893: ...by the channel right CHSIDE has no meaning for the PCM protocol Four data and packet frames are available Data may be sent with a format of 16 bit data packed in 16 bit frame 16 bit data packed in 32...

Страница 894: ...ver The WS signal is also latched on the falling edge of CK Figure 265 I2 S Philips standard waveforms 24 bit frame with CPOL 0 This mode needs two write or read operations to from the SPI_DR In trans...

Страница 895: ...ing bits are forced by hardware to 0x0000 to extend the data to 32 bit format If the data to transmit or the received data are 0x76A3 0x76A30000 extended to 32 bit the operation shown in Figure 269 is...

Страница 896: ...MSB half word is received In this way more time is provided between two write or read operations which prevents underrun or overrun conditions depending on the direction of the data transfer MSB just...

Страница 897: ...tified standard no difference for the 16 bit and 32 bit full accuracy frame formats Figure 273 LSB justified 16 bit or 32 bit full accuracy with CPOL 0 CK WS SD Channel left 32 bit Channel right MSB L...

Страница 898: ...re required on each RXNE event Figure 276 Operations required to receive 0x3478AE CK WS SD Channel left 32 bit Channel right MSB LSB 24 bit remaining 0 forced 8 bit data Transmission Reception 0xXX34...

Страница 899: ...ion shown in Figure 278 is required Figure 278 Example of LSB justified 16 bit extended to 32 bit packet frame In transmission mode when TXE is asserted the application has to write the data to be tra...

Страница 900: ...in master mode For short frame synchronization the WS synchronization signal is only one cycle long Figure 280 PCM standard waveforms 16 bit extended to 32 bit packet frame Note For both modes master...

Страница 901: ...tecture 1 Where x could be 2 or 3 Figure 281 presents the communication clock architecture To achieve high quality audio performance the I2SxCLK clock source can be either the PLLI2S output through R...

Страница 902: ...6 bit 256 2 62 1 32000 0 0000 32 bit 256 5 12 1 32000 0 0000 48000 16 bit 192 5 12 1 48000 0 0000 32 bit 384 5 12 1 48000 0 0000 96000 16 bit 384 5 12 1 96000 0 0000 32 bit 424 3 11 1 96014 49219 0 01...

Страница 903: ...irection Transmitter or Receiver through the I2SCFG 1 0 bits in the SPI_I2SCFGR register 4 If needed select all the potential interruption sources and the DMA capabilities by writing the SPI_CR2 regis...

Страница 904: ...mode selected refer to Section 28 4 3 Supported audio protocols If data are received while the previously received data have not been read yet an overrun is generated and the OVR flag is set If the E...

Страница 905: ...fied and LSB justified modes the first data item to be written into the data register corresponds to the data for the left channel When the communication starts the data are transferred from the Tx bu...

Страница 906: ...to the external WS line managed by the external master component Clearing the RXNE bit is performed by reading the SPI_DR register For more details about the read operations depending the I2 S standa...

Страница 907: ...ates the channel side to which the data to transfer on SD has to belong In case of an underrun error event in slave transmission mode this flag is not reliable and I2 S needs to be switched off and sw...

Страница 908: ...ost to recover from this state and resynchronize the external master device with the I2S slave device follow the steps below 1 Disable the I2S 2 Re enable it when the correct level is detected on the...

Страница 909: ...bled transmit only mode Note This bit is not used in I2 S mode In master mode the MOSI pin is used while the MISO pin is used in slave mode Bit 13 CRCEN Hardware CRC calculation enable 0 CRC calculati...

Страница 910: ...in I2 S mode and SPI TI mode Bit 8 SSI Internal slave select This bit has an effect only when the SSM bit is set The value of this bit is forced onto the NSS pin and the IO value of the NSS pin is ign...

Страница 911: ...ot used in I2 S mode and SPI TI mode 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved TXEIE RXNEIE ERRIE FRF Res SSOE TXDMAEN RXDMAEN rw rw rw rw rw rw rw Bits 15 8 Reserved must be kept at reset value...

Страница 912: ...TXE RXNE r r r r rc_w0 r r r r Bits 15 9 Reserved Forced to 0 by hardware Bit 8 FRE Frame format error 0 No frame format error 1 A frame format error occurred This flag is set by hardware and cleared...

Страница 913: ...pty 1 Tx buffer empty Bit 0 RXNE Receive buffer not empty 0 Rx buffer empty 1 Rx buffer not empty 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 DR 15 0 rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw Bits 15...

Страница 914: ...10 9 8 7 6 5 4 3 2 1 0 RXCRC 15 0 r r r r r r r r r r r r r r r r Bits 15 0 RXCRC 15 0 Rx CRC register When CRC calculation is enabled the RxCRC 15 0 bits contain the computed CRC value of the subseq...

Страница 915: ...16 standard Note A read to this register when the BSY flag is set could return an incorrect value These bits are not used for I2 S mode 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved I2SMOD I2SE I2SCF...

Страница 916: ...eady state is high level Note For correct operation this bit should be configured when the I2 S is disabled This bit is not used in SPI mode Bits 2 1 DATLEN Data length to be transferred 00 16 bit dat...

Страница 917: ...ot used in SPI mode Bit 8 ODD Odd factor for the prescaler 0 real divider value is I2SDIV 2 1 real divider value is I2SDIV 2 1 Refer to Section 28 4 4 on page 901 Not used in SPI mode Note This bit sh...

Страница 918: ...0 0 0x04 SPI_CR2 Reserved TXEIE RXNEIE ERRIE FRF Reserved SSOE TXDMAEN RXDMAEN Reset value 0 0 0 0 0 0 0 0x08 SPI_SR Reserved FRE BSY OVR MODF CRCERR UDR CHSIDE TXE RXNE Reset value 0 0 0 0 0 0 0 1 0...

Страница 919: ...mple To bring this level of flexibility and configurability the SAI contains two audio sub blocks that are fully independent of each other Each audio sub block is connected to up to 4 pins SD SCK FS M...

Страница 920: ...M DSP TDM AC 97 Up to 16 slots available with configurable size and with the possibility to select which ones are active in the audio frame Number of bits by frame may be configurable Frame synchroniz...

Страница 921: ...pin and eventually an MCLK pin making them general purpose I Os The functional state machine can be configured to address a wide range of audio protocols Some registers are present to set up the desir...

Страница 922: ...nt audio block The I O pin SD will be defined respectively as an output or an input It is possible to declare two master audio blocks in the same SAI with two different MCLK and SCK clock frequencies...

Страница 923: ...EN 1 0 00 in SAI_xCR1 and the other one declared as synchronous with the other audio block respective bit SYNCEN 1 0 01 in the SAI_xCR1 Note APB frequency PCLK must be greater or equal to twice the bi...

Страница 924: ...e frame length should be aligned to a number equal to a power of 2 from 8 to 256 This is to ensure that an audio frame contains an integer number of MCLK pulses per bit clock which ensures correct ope...

Страница 925: ...er makes the choice 29 7 5 FS signal role The FS signal may have a different meaning depending on the FS function Bit FSDEF in the SAI_xFRCR register selects which meaning it will have It may be eithe...

Страница 926: ...he transfer of these remaining bits In reception mode these bits are discarded Figure 286 FS role is start of frame FSDEF 0 29 8 Slot configuration The slot is the basic element in the audio frame The...

Страница 927: ...configuration with FBOFF 0 in SAI_xSLOTR It is possible to choose the position of the first data bit to transfer within the slots this offset is configured by bit FBOFF 5 0 in the SAI_xSLOTR register...

Страница 928: ...k generator is OFF Figure 289 illustrates the architecture of the audio block clock generator Figure 289 Audio block clock generator overview Note If NoDiv is set to 1 the MCLK_x signal will be set at...

Страница 929: ...SCK_x The SAI_CK_x clock can be also equal to the bit clock frequency In this case bit NODIV in the SAI_xCR1 register should be set and the value inside the MCKDIV divider and the bit clock divider wi...

Страница 930: ...an 011b This Interrupt FREQ bit in SAI_XSR register is cleared by hardware when at least half of the FIFO contains data FLTH 2 0 bits in SAI_xSR are higher or equal to 011b When the FIFO threshold bit...

Страница 931: ...XSR register is cleared by hardware when the FIFO has less than three quarters of the FIFO data locations avalable FLTH 2 0 bits in SAI_xSR is less than 100b When the FIFO threshold bits in SAI_XCR2 r...

Страница 932: ...cally as an output since the AC 97 controller link drives the FS signal whatever the master or slave configuration Figure 290 presents an AC 97 audio frame structure Figure 290 AC 97 audio frame Note...

Страница 933: ...was present in the FIFO and for which the Mute mode is requested is discarded Receiver In receiver mode it is possible to detect a Mute mode sent from the external transmitter when all the declared a...

Страница 934: ...andard employed in the United States and Japan is the Law and allows 14 bits of dynamic range COMP 1 0 10 in the SAI_xCR2 register The European companding standard is A Law and allows 13 bits of dynam...

Страница 935: ...is transmitted or The line is released in HI z state at the end of the last bit of data transferred to release the line for other transmitters connected to this node It is important to note that the...

Страница 936: ...FSDEF 1 and half frame length number of slots 2 and NBSLOT 6 VORW XGLR IUDPH LW 75 6 LQ WKH 6 B 5 DQG IUDPH OHQJWK QXPEHU RI VORWV 06 9 6ORW VL H GDWD VL H 6ORW VL H GDWD VL H LW 75 6 LQ WKH 6 B 5 DQG...

Страница 937: ...transmitter and each audio block in an SAI has its own SAI_xSR register Overrun When the audio block is configured as receiver an overrun condition may appear if data is received in an audio frame whe...

Страница 938: ...Proceed as follows 1 Disable the SAI peripheral by resetting the SAIEN bit of the SAI_xCR1 register Check that the SAI has been disabled by reading back the SAIEN bit SAIEN should be equal to 0 2 Flus...

Страница 939: ...it in SAI_xCR1 register to be sure that the SAI is disabled SAIEN bit is should be equal to 0 reading back this bit 2 FIFO should be flushed via FFLUS bit in SAI_xCR2 register 3 Re enabling the SAI pe...

Страница 940: ...is set It is asserted when the codec is not ready to communicate during the reception of the TAG 0 slot0 of the AC 97 audio frame In this case there will be no data automatically stored into the FIFO...

Страница 941: ...pt group Audio block mode Interrupt enable Interrupt clear FREQ FREQ Master or Slave Receiver or transmitter FREQIE in SAI_xIM register Depend on FIFO threshold setting FLTH bits in SAI_CR2 Communicat...

Страница 942: ...the SAI_xCR1 register The DMA request is managed directly by the FIFO controller depend of FIFO threshold level for more details please refer to Internal FIFOs section DMA direction is linked to the S...

Страница 943: ...DMAEN DMA enable This bit is set and cleared by software 0 DMA is disabled 1 DMA is enabled Note In receiver mode the bits MODE must be configured before setting bit DMAEN to avoid a DMA request since...

Страница 944: ...This bit is set and cleared by software 0 data strobing edge is falling edge of SCK 1 data strobing edge is rising edge of SCK This bit has to be configured when the audio block is disabled Bit 8 LSBF...

Страница 945: ...ss a specific audio protocol like I2S LSB MSB justified TDM PCM DSP setting most of the configuration register bits as well as frame configuration register These bits have to be configured when the au...

Страница 946: ...e state of bit MODE 0 The data compression is applied if the audio block is configured as a transmitter The data expansion is automatically applied when the audio block is configured as a receiver Ref...

Страница 947: ...value if the number of slots is lower or equal to 2 or equal to 0 if it is greater than 2 Refer to Section 29 12 1 for more details Bit 4 TRIS Tristate management on data line This bit is set and clea...

Страница 948: ...audio block is disabled Bit 17 FSPOL Frame synchronization polarity This bit is set and cleared by software 0 FS is active low falling edge 1 FS is active high rising edge This bit is used to configu...

Страница 949: ...More precisely these bits define the number of SCK clocks for each audio frame The number of bits in the frame is equal to FRL 7 0 1 The minimum number of bits to transfer in an audio frame has to be...

Страница 950: ...t FSDEF in the SAI_AFRCR register is set If the size is greater than the data size the remaining bits will be forced to 0 if bit TRIS in the SAI_xCR1 register is clear otherwise they will be forced to...

Страница 951: ...upt is disabled 1 Interrupt is enabled When this bit is set an interrupt will be generated if the AFSDET bit in the SAI_ASR register is set This bit has no meaning in AC 97 mode It has no meaning also...

Страница 952: ...t Note This bit is used only in TDM mode and has no meaning for other modes Bit 1 MUTEDETIE Mute detection interrupt enable This bit is set and cleared by software 0 Interrupt is disabled 1 Interrupt...

Страница 953: ...figured as receiver 000 FIFO_empty 001 FIFO but not empty 010 FIFO 011 FIFO 100 FIFO but not full 101 FIFO full Bits 15 7 Reserved always read as 0 Bit 6 LFSDET Late frame synchronization detection Th...

Страница 954: ...configuration of FRL 7 0 bit in the SAI_x FRCR register This bit is used only when the audio block is master MODE 1 0 in the SAI_xCR1 register and when NODIV 0 in the SAI_xCR1 register It may generate...

Страница 955: ...used in AC 97 Reading this bit always returns the value 0 Bit 4 CCNRDY Clear codec not ready flag This bit is write only Writing 1 in this bit clears the flag CNRDY in the SAI_xSR register This bit is...

Страница 956: ...31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0x0004 or 0x0024 SAI_xCR1 Reserved MCJDIV 3 0 NODIV Res DMAEN SAIxEN Reserved OutDri MONO SYNCE N 1 0 CKSTR LSBFIR...

Страница 957: ...served LFSDET CAFSDET CNRDY Res WCKCFG MUTEDET OVRUDR Reset value 0 0 0 0 0 0 0x0020 or 0x0040 SAI_xDR DATA 31 0 Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Table 131 S...

Страница 958: ...Full duplex asynchronous communications NRZ standard format Mark Space Configurable oversampling method by 16 or by 8 to give flexibility between speed and clock tolerance Fractional baud rate generat...

Страница 959: ...e up from mute mode by idle line detection or address mark detection Two receiver wakeup modes Address bit MSB 9th bit Idle line 30 3 USART functional description The interface is externally connected...

Страница 960: ...6 USART registers on page 999 for the definitions of each bit The following pin is required to interface in synchronous mode SCLK Transmitter clock output This pin outputs the transmitter data clock...

Страница 961: ...ister DR Transmitter clock Receiver clock Receiver rate Transmitter rate fPCLKx x 1 2 control control 8 x 2 OVER8 Conventional baudrate generator SBK RWU RE TE IDLE RXNE TCIE TXEIE CR1 UE PCE PS PEIE...

Страница 962: ...ither 1 or 2 stop bits logic 1 bit to acknowledge the start bit Transmission and reception are driven by a common baud rate generator the clock for each is generated when the enable bit is set respect...

Страница 963: ...2 stop bits Note The TE bit should not be reset during transmission of data Resetting the TE bit during the transmission will corrupt the data on the TX pin as the baud rate counters will get frozen...

Страница 964: ...is disabled or enters the Halt mode to avoid corrupting the last transmission Single byte communication Clearing the TXE bit is always performed by a write to the data register The TXE bit is set by...

Страница 965: ...ion Figure 299 TC TXE behavior when transmitting Break characters Setting the SBK bit transmits a break character The break frame length depends on the M bit see Figure 297 If the SBK bit is set to 1...

Страница 966: ...nds the 3 bits at 0 and second sampling on the 8th 9th and 10th bits also finds the 3 bits at 0 The start bit is validated RXNE flag set interrupt generated if RXNEIE 1 but the NE noise flag is set if...

Страница 967: ...indicates that the content of the shift register is transferred to the RDR In other words data has been received and can be read as well as its associated error flags An interrupt is generated if the...

Страница 968: ...ta is stored in the receive register RDR and can be read if RXNE 0 then it means that the last valid data has already been read and thus there is nothing to be read in the RDR This case can occur when...

Страница 969: ...eceiver s tolerance to clock deviations see Section 30 3 5 USART receiver tolerance to clock deviation on page 981 In this case the NF bit will never be set When noise is detected in a frame The NF bi...

Страница 970: ...er to the USART_DR register No interrupt is generated in case of single byte communication However this bit rises at the same time as the RXNE bit which itself generates an interrupt In case of multib...

Страница 971: ...one 0 5 baud clock period during which nothing happens followed by 1 normal stop bit period during which sampling occurs halfway through Refer to Section 30 3 11 Smartcard on page 990 for more detail...

Страница 972: ...BRR 0x19A hence USARTDIV 0d25 625 Example 3 To program USARTDIV 0d50 99 This leads to DIV_Fraction 16 0d0 99 0d15 84 The nearest real number is 0d16 0x10 overflow of DIV_frac 3 0 carry must be added u...

Страница 973: ...Error Calculated Desired B rate Desired B rate Actual Value programmed in the baud rate register Error 1 1 2 KBps 1 2 KBps 416 6875 0 1 2 KBps 625 0 2 2 4 KBps 2 4 KBps 208 3125 0 01 2 4 KBps 312 5 0...

Страница 974: ...4 KBps 228 571 KBps 4 375 0 79 230 769 KBps 6 5 0 16 9 460 8 KBps 470 588 KBps 2 125 2 12 461 538 KBps 3 25 0 16 10 921 6 KBps 888 889 KBps 1 125 3 55 923 077 KBps 1 625 0 16 11 2 MBps NA NA NA NA NA...

Страница 975: ...calculation for programmed baud rates at fPCLK 16 MHz or fPCLK 24 MHz oversampling by 8 1 Oversampling by 8 OVER8 1 Baud rate fPCLK 16 MHz fPCLK 24 MHz S No Desired Actual Value programmed in the baud...

Страница 976: ...0 8 KBps 470 588 KBps 1 0625 2 12 457 143 KBps 2 1875 0 79 8 896 KBps NA NA NA 888 889 KBps 1 1250 0 79 9 921 6 KBps NA NA NA 941 176 KBps 1 0625 2 12 10 1 792 MBps NA NA NA NA NA NA 11 1 8432 MBps NA...

Страница 977: ...ed baud rates at fPCLK 8 MHz or fPCLK 16 MHz oversampling by 8 1 continued Oversampling by 8 OVER8 1 Baud rate fPCLK 8 MHz fPCLK 16 MHz S No Desired Actual Value programmed in the baud rate register E...

Страница 978: ...rsampling by 16 1 2 continued Oversampling by 16 OVER8 0 Baud rate fPCLK 30 MHz fPCLK 60 MHz S No Desired Actual Value programme d in the baud rate register Error Calculated Desired B Rate Desired B R...

Страница 979: ...sampling by 8 OVER8 1 Baud rate fPCLK 30 MHz fPCLK 60 MHz S No Desired Actual Value programme d in the baud rate register Error Calculated Desired B Rate Desired B Rate Actual Value programmed in the...

Страница 980: ...LK 84 Hz oversampling by 16 1 2 continued Oversampling by 16 OVER8 0 Baud rate fPCLK 42 MHz fPCLK 84 MHz S No Desired Actual Value programme d in the baud rate register Error Calculated Desired B Rate...

Страница 981: ...43 KBps 5 75 0 93 923 076 KBps 11 375 0 93 11 1 792 MBps 1 826 MBps 2 875 1 9 1 787Mbps 5 875 0 27 12 1 8432 MBps 1 826 MBps 2 875 0 93 1 826 MBps 5 75 0 93 13 3 584 MBps 3 5 MBps 1 5 2 34 3 652 MBps...

Страница 982: ...their respective TX outputs are logically ANDed together and connected to the RX input of the master In multiprocessor configurations it is often desirable that only the intended message recipient sh...

Страница 983: ...ess which is programmed in the ADD bits in the USART_CR2 register The USART enters mute mode when an address character is received which does not match its programmed address In this case the RWU bit...

Страница 984: ...de of the 7 or 8 LSB bits depending on whether M is equal to 0 or 1 and the parity bit E g data 00110101 4 bits set parity bit will be 1 if odd parity is selected PS bit in USART_CR1 1 Parity checking...

Страница 985: ...et the LINEN bit to enter LIN mode In this case setting the SBK bit sends 13 0 bits as a break character Then a bit of value 1 is sent to allow the next start detection LIN reception A break detection...

Страница 986: ...not long enough break discarded LBD is not set Break Frame RX line Break State machine Capture Strobe 0 Bit1 Bit2 Bit3 Bit4 Bit5 Bit6 Bit7 Bit8 Bit9 Idle Idle Read Samples Bit0 0 0 0 0 0 0 0 0 0 1 Bit...

Страница 987: ...r to select the phase of the external clock see Figure 307 Figure 308 Figure 309 During the Idle state preamble and send break the external SCLK clock is not activated In synchronous mode the USART tr...

Страница 988: ...ame instruction in order to minimize the setup and the hold time of the receiver The USART supports master mode only it cannot receive or send data related to an input clock SCLK is always an output F...

Страница 989: ...tween half and full duplex communication is made with a control bit HALF DUPLEX SEL HDSEL in USART_CR3 As soon as HDSEL is written to 1 the TX and RX lines are internally connected the RX pin is no lo...

Страница 990: ...stop bits for both transmitting and receiving to avoid switching between the two configurations Figure 311 shows examples of what can be seen on the data line with and without parity error Figure 311...

Страница 991: ...periods On the receiver side if a parity error is detected and a NACK is transmitted the receiver will not detect the NACK as a start bit Note A break character is not significant in Smartcard mode A...

Страница 992: ...the IrDA encoder any data on the IrDA receive line will be ignored by the IrDA decoder and if the Receiver is busy USART is receiving decoded data from the USART data on the TX from the USART to IrDA...

Страница 993: ...RT should discard pulses of duration shorter than 1 PSC A valid low is accepted only if its duration is greater than 2 periods of the IrDA low power Baud clock PSC value in USART_GTPR Note A pulse of...

Страница 994: ...igure it as the source of the transfer The data will be loaded into the USART_DR register from this memory area after each TXE event 3 Configure the total number of bytes to be transferred to the DMA...

Страница 995: ...RXNE event 3 Configure the total number of bytes to be transferred in the DMA control register 4 Configure the channel priority in the DMA control register 5 Configure interrupt generation after half...

Страница 996: ...current byte with either of these errors 30 3 14 Hardware flow control It is possible to control the serial data flow between 2 devices by using the nCTS input and the nRTS output The Figure 317 shows...

Страница 997: ...se the transmission does not occur When nCTS is deasserted during a transmission the current transmission is completed before the transmitter stops When CTSE 1 the CTSIF status bit is automatically se...

Страница 998: ...only in multi buffer communication These events generate an interrupt if the corresponding Enable Control Bit is set Figure 320 USART interrupt mapping diagram Table 146 USART interrupt requests Inte...

Страница 999: ...Reset value 0x00C0 0000 Table 147 USART mode configuration 1 1 X supported NA not applicable USART modes USART 1 USART 2 USART 3 UART4 UART5 USART 6 Asynchronous mode X X X X X X Hardware flow control...

Страница 1000: ...ransmission Bit 6 TC Transmission complete This bit is set by hardware if the transmission of a frame containing data is complete and if TXE is set An interrupt is generated if TCIE 1 in the USART_CR1...

Страница 1001: ...i Buffer communication if the EIE bit is set Note When the line is noise free the NF flag can be disabled by programming the ONEBIT bit to 1 to increase the USART tolerance to deviations Refer to Sect...

Страница 1002: ...between the input shift register and the internal bus When transmitting with the parity enabled PCE bit set to 1 in the USART_CR1 register the value written in the MSB bit 7 or bit 8 depending on the...

Страница 1003: ...0 Idle Line 1 Address Mark Bit 10 PCE Parity control enable This bit selects the hardware parity control generation and detection When the parity control is enabled the computed parity is inserted at...

Страница 1004: ...he transmission starts Bit 2 RE Receiver enable This bit enables the receiver It is set and cleared by software 0 Receiver is disabled 1 Receiver is enabled and begins searching for a start bit Bit 1...

Страница 1005: ...op bit Note The 0 5 Stop bit and 1 5 Stop bit are not available for UART4 UART5 Bit 11 CLKEN Clock enable This bit allows the user to enable the SCLK pin 0 SCLK pin disabled 1 SCLK pin enabled This bi...

Страница 1006: ...errupt is inhibited 1 An interrupt is generated whenever LBD 1 in the USART_SR register Bit 5 LBDL lin break detection length This bit is for selection between 11 bit or 10 bit break detection 0 10 bi...

Страница 1007: ...rrent character has been transmitted The nRTS output is asserted tied to 0 when a data can be received Note This bit is not available for UART4 UART5 Bit 7 DMAT DMA enable transmitter This bit is set...

Страница 1008: ...cleared by software 0 IrDA disabled 1 IrDA enabled Bit 0 EIE Error interrupt enable Error Interrupt Enable Bit is required to enable interrupt generation in case of a framing error overrun error or n...

Страница 1009: ...r mode PSC 7 0 IrDA Low Power Baud Rate Used for programming the prescaler for dividing the system clock to achieve the low power frequency The source clock is divided by the value given in the regist...

Страница 1010: ...e 0 0 1 1 0 0 0 0 0 0 0x04 USART_DR Reserved DR 8 0 Reset value 0 0 0 0 0 0 0 0 0 0x08 USART_BRR Reserved DIV_Mantissa 15 4 DIV_Fraction 3 0 Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0x0C USART_CR1...

Страница 1011: ...pport for two different databus modes 1 bit default and 4 bit Full support of the CE ATA features full compliance with CE ATA digital protocol Rev1 1 Data transfer up to 48 MHz for the 8 bit mode Data...

Страница 1012: ...rom MMC are done data blocks or streams Data transfers to from the CE ATA Devices are done in data blocks Figure 321 SDIO no response and no data operations Figure 322 SDIO multiple block read operati...

Страница 1013: ...ard to host Data from host to card Stop command stops data transfer Optional cards Busy Needed for CE ATA Command Response Command Response Data block crc Busy Busy Data block crc Busy SDIO_CMD SDIO_D...

Страница 1014: ...bus data transfer can be configured by the host to use SDIO_D0 or SDIO_D 3 0 All data lines are operating in push pull mode SDIO_CMD has two operational modes Open drain for initialization only for M...

Страница 1015: ...e SDIO adapter clock domain SDIOCLK Adapter register block The adapter register block contains all system registers This block also generates the signals that clear the static flags in the multimedia...

Страница 1016: ...us output signals during the power off and power up phases The clock management subunit generates and controls the SDIO_CK signal The SDIO_CK output can use either the clock divide or the clock bypass...

Страница 1017: ...e command path state machine CPSM sets the status flags and enters the Idle state if a response is not required If a response is required it waits for the response see Figure 330 on page 1018 When the...

Страница 1018: ...Send state This enables the data counter to trigger the stop command transmission Note The CPSM remains in the Idle state for at least eight SDIO_CK periods to meet the NCC and NRC timing constraints...

Страница 1019: ...he SDIO_CMD output is in the Hi Z state as shown in Figure 331 on page 1019 Data on SDIO_CMD are synchronous with the rising edge of SDIO_CK Table shows the command format Response a response is a tok...

Страница 1020: ...ransmitter bit and the six reserved bits are not used in the CRC calculation The CRC checksum is a 7 bit value CRC 6 0 Remainder M x x7 G x G x x7 x3 1 M x start bit x39 last bit before CRC x0 or M x...

Страница 1021: ...the transfer direction send or receive the data path state machine DPSM moves to the Wait_S or Wait_R state when it is enabled Send the DPSM moves to the Wait_S state If there is data in the transmit...

Страница 1022: ...e when the data block counter reaches zero the DPSM waits until it receives the CRC code If the received code matches the internally generated CRC code the DPSM moves to the Wait_R state If not the CR...

Страница 1023: ...e state Busy the DPSM waits for the CRC status flag If it does not receive a positive CRC status it moves to the Idle state and sets the CRC fail status flag If it receives a positive CRC status it mo...

Страница 1024: ...its shift register it increments the read pointer and drives new data out If the transmit FIFO is disabled all status flags are deasserted The data path subunit asserts TXACT when it transmits data Re...

Страница 1025: ...to an MMC 512 bytes using CMD24 WRITE_BLOCK The SDIO FIFO is filled by data stored in a memory using the DMA controller 1 Do the card identification process 2 Increase the SDIO_CK frequency 3 Select...

Страница 1026: ...ta control register DTEN with 1 SDIO card host enabled to send data DTDIR with 0 from controller to card DTMODE with 0 block data transfer DMAEN with 1 DMA enabled DBLOCKSIZE with 0x9 512 bytes Other...

Страница 1027: ...iffers for MultiMediaCards and SD cards For MultiMediaCard cards the identification process starts at clock rate Fod The SDIO_CMD line output drivers are open drain and allow parallel card operation d...

Страница 1028: ...rom the host to the card with a CRC appended to the end of each block by the host A card supporting block write is always able to accept a block of data defined by WRITE_BL_LEN If the CRC fails the ca...

Страница 1029: ...he data state The host must than abort the operation by sending the stop transmission command The read error is reported in the response to the stop transmission command If the host sends a stop trans...

Страница 1030: ...send its data starting at a specified address until the SDIO card host sends STOP_TRANSMISSION CMD12 The stop command has an execution delay due to the serial command transmission and the data transfe...

Страница 1031: ...egister is set The card indicates that an erase is in progress by holding SDIO_D low The actual erase time may be quite long and the host may issue CMD7 to deselect the card 31 4 9 Wide bus selection...

Страница 1032: ...cated by a nonzero value of PWD_LEN the card is locked automatically after power up As with the CSD and CID register write commands the lock unlock commands are available in the transfer state only In...

Страница 1033: ...rd lock unlock mode the 8 bit PWD_LEN and the number of bytes in the currently used password 3 Send LOCK UNLOCK CMD42 with the appropriate data block size on the data line including the 16 bit CRC The...

Страница 1034: ...ard fails and the LOCK_UNLOCK_FAILED error bit is set in the card status register Forcing erase If the user has forgotten the password PWD content it is possible to access the card after clearing all...

Страница 1035: ..._MISALIGN 0 no error 1 error The commands address argument in accordance with the currently set block length positions the first data block misaligned to the card physical blocks A multiple block read...

Страница 1036: ...the standard A generic card error related to the and detected during execution of the last host command e g read or write failures C 18 Reserved 17 Reserved 16 CID CSD_OVERWRITE E X 0 no error 1 erro...

Страница 1037: ...us command to read these bits 12 9 CURRENT_STATE S R 0 Idle 1 Ready 2 Ident 3 Stby 4 Tran 5 Data 6 Rcv 7 Prg 8 Dis 9 Btst 10 15 reserved The state of the card when receiving the command If the command...

Страница 1038: ...are The following cards are currently defined 0000 Regular SD RD WR Card 0001 SD ROM Card In the future the 8 LSBs will be used to define different variations of an SD memory card each bit will define...

Страница 1039: ...OF_PROTECTED_AREA SIZE_OF_PROTECTED_AREA is specified by the unit in bytes SPEED_CLASS This 8 bit field indicates the speed class and the value can be calculated by PW 2 where PW is the write performa...

Страница 1040: ...er to ERASE_TIMEOUT The host should determine the proper number of AUs to be erased in one operation so that the host can show the progress of the erase operation If this field is set to 0 the erase t...

Страница 1041: ...upt to the MultiMediaCard SD module The use of the interrupt is optional for each card or function within a card The SD I O interrupt is level sensitive which means that the interrupt line must be hel...

Страница 1042: ...efined only for the SD 1 bit and 4 bit modes The ReadWait operation allows the MMC SD module to signal a card that it is reading multiple registers IO_RW_EXTENDED CMD53 to temporarily stall the data t...

Страница 1043: ...ormat and meaning The card must be selected in transfer state before sending GEN_CMD CMD56 The data block size is defined by SET_BLOCKLEN CMD16 The response to GEN_CMD CMD56 is in R1b format Command t...

Страница 1044: ...1b SET_WRITE_PROT If the card has write protection features this command sets the write protection bit of the addressed group The properties of write protection are coded in the card specific data WP_...

Страница 1045: ...ressed register This command accesses application dependent registers that are not defined in the MultiMediaCard standard CMD40 bcr 31 0 stuff bits R5 GO_IRQ_STATE Places the system in the interrupt m...

Страница 1046: ...Code length 48 bits The 45 40 bits indicate the index of the command to be responded to this value being interpreted as a binary coded number between 0 and 63 The status of the card is coded in 32 bit...

Страница 1047: ...busy low 31 5 5 R4 Fast I O Code length 48 bits The argument field contains the RCA of the addressed card the register address to be read from or written to and its content Table 173 R2 response Bit...

Страница 1048: ...would detect the CMD5 as an illegal command and not respond The I O aware host will send CMD5 If the card responds with response R4 the host determines the card s configuration based on the data conta...

Страница 1049: ...wait operation by stopping the clock SDIO suspend resume operation write and read suspend SDIO interrupts The SDIO supports these operations only if the SDIO_DCTRL 11 bit is set except for read suspe...

Страница 1050: ...ead wait by stopping SDIO_CK SDIO_DCTRL is set just like in the method presented in Section 31 6 1 but SDIO_DCTRL 10 1 DSPM stops the clock two SDIO_CK cycles after the end bit of the current received...

Страница 1051: ...trigger moves the CPSM to the Send state When the command counter reaches 48 the CPSM becomes Idle as no response is awaited 31 7 2 Command completion signal enable If the enable CMD completion bit S...

Страница 1052: ...ce communicates to the system via 32 bit wide control registers accessible via APB2 The peripheral registers have to be accessed by words 32 bits 31 9 1 SDIO power control register SDIO_POWER Address...

Страница 1053: ...0b SDIO_CK generated on the rising edge of the master clock SDIOCLK 1b SDIO_CK generated on the falling edge of the master clock SDIOCLK Bits 12 11 WIDBUS Wide bus mode enable bit 00 Default bus mode...

Страница 1054: ...d wait interval for SD I O cards in this case the SDIO_CLKCR register does not control SDIO_CK 31 9 3 SDIO argument register SDIO_ARG Address offset 0x08 Reset value 0x0000 0000 The SDIO_ARG register...

Страница 1055: ...set the CPSM transfers CMD61 Bit 13 nIEN not Interrupt Enable if this bit is 0 interrupts in the CE ATA device are enabled Bit 12 ENCMDcompl Enable CMD completion If this bit is set the command comple...

Страница 1056: ...gisters contain the status of a card which is part of the received response The Card Status size is 32 or 127 bits depending on the response type The most significant bit of the card status is receive...

Страница 1057: ...value is loaded into the data counter when data transfer starts Note For a block data transfer the value in the data length register must be a multiple of the block size see SDIO_DCTRL A data transfe...

Страница 1058: ...WSTART bit is set 1 Enable for read wait stop if RWSTART bit is set Bit 8 RWSTART Read wait start If this bit is set read wait operation starts Bits 7 4 DBLOCKSIZE Data block size Define the data bloc...

Страница 1059: ...te This register should be read only when the data transfer is complete Bit 2 DTMODE Data transfer mode selection 1 Stream or SDIO multibyte data transfer 0 Block data transfer 1 Stream or SDIO multib...

Страница 1060: ...value Bit 23 CEATAEND CE ATA command completion signal received for CMD61 Bit 22 SDIOIT SDIO interrupt received Bit 21 RXDAVL Data available in receive FIFO Bit 20 TXDAVL Data available in transmit FI...

Страница 1061: ...1 0 Reserved CEATAENDC SDIOITC Reserved DBCKENDC STBITERRC DATAENDC CMDSENTC CMDRENDC RXOVERRC TXUNDERRC DTIMEOUTC CTIMEOUTC DCRCFAILC CCRCFAILC rw rw rw rw rw rw rw rw rw rw rw rw rw Bits 31 24 Reser...

Страница 1062: ...cleared Bit 4 TXUNDERRC TXUNDERR flag clear bit Set by software to clear TXUNDERR flag 0 TXUNDERR not cleared 1 TXUNDERR cleared Bit 3 DTIMEOUTC DTIMEOUT flag clear bit Set by software to clear the D...

Страница 1063: ...le Set and cleared by software to enable disable the interrupt generated when receiving the SDIO mode interrupt 0 SDIO Mode Interrupt Received interrupt disabled 1 SDIO Mode Interrupt Received interru...

Страница 1064: ...et and cleared by software to enable disable interrupt caused by data being transferred data transmit acting 0 Data transmit acting interrupt disabled 1 Data transmit acting interrupt enabled Bit 11 C...

Страница 1065: ...error interrupt enable Set and cleared by software to enable disable interrupt caused by Tx FIFO underrun error 0 Tx FIFO underrun error interrupt disabled 1 Tx FIFO underrun error interrupt enabled...

Страница 1066: ...w rw rw rw bits 31 0 FIFOData Receive and transmit FIFO data The FIFO data occupies 32 entries of 32 bit words from address SDIO base 0x080 to SDIO base 0xFC Table 180 SDIO register map Offset Registe...

Страница 1067: ...TBITERRC DATAENDC CMDSENTC CMDRENDC RXOVERRC TXUNDERRC DTIMEOUTC CTIMEOUTC DCRCFAILC CCRCFAILC 0x3C SDIO_MASK Reserved CEATAENDIE SDIOITIE RXDAVLIE TXDAVLIE RXFIFOEIE TXFIFOEIE RXFIFOFIE TXFIFOFIE RXF...

Страница 1068: ...all hardware functions for supporting the CAN Time Triggered Communication option 32 2 bxCAN main features Supports CAN protocol version 2 0 A B Active Bit rates up to 1 Mbit s Supports the Time Trigg...

Страница 1069: ...and Diagnostic messages have been introduced An enhanced filtering mechanism is required to handle each type of message Furthermore application tasks require more CPU time therefore real time constra...

Страница 1070: ...e transmit mailboxes are provided to the software for setting up messages The transmission Scheduler decides which mailbox has to be transmitted first 32 3 4 Acceptance filters The bxCAN provides 28 s...

Страница 1071: ...AK nor SLAK are set bxCAN is in normal FFHSWDQFH LOWHUV LOWHU 7UDQVPLVVLRQ 6FKHGXOHU 0DLOER 5 HFHLYH 2 0DLOER 5H FHLYH 2 0DLOER 7 0DLOER HV 7UDQVPLVVLRQ 6FKHGXOHU 0DLOER 5H FHLYH 2 0DLOER 5 HFHLYH 2 0...

Страница 1072: ...he filter values also can be modified by deactivating the associated filter activation bits in the CAN_FA1R register If a filter bank is not used it is recommended to leave it non active leave the cor...

Страница 1073: ...Figure 336 bxCAN operating modes 1 ACK The wait state during which hardware confirms a request by setting the INAK or SLAK bits in the CAN_MSR register 2 SYNC The state during which bxCAN waits until...

Страница 1074: ...ternal events the CAN Core ignores acknowledge errors no dominant bit sampled in the acknowledge slot of a data remote frame in Loop Back Mode In this mode the bxCAN performs an internal feedback from...

Страница 1075: ...Immediately after the TXRQ bit has been set the mailbox enters pending state and waits to become the highest priority mailbox see Transmit Priority As soon as the mailbox has the highest priority it w...

Страница 1076: ...ent transmission Nonautomatic retransmission mode This mode has been implemented in order to fulfil the requirement of the Time Triggered Communication option of the CAN standard To configure the hard...

Страница 1077: ...ave CPU load simplify the software and guarantee data consistency the FIFO is managed completely by hardware The application accesses the messages stored in the FIFO through the FIFO output mailbox Va...

Страница 1078: ...isabled RFLM bit in the CAN_MCR register cleared the last message stored in the FIFO will be overwritten by the new incoming message In this case the latest messages will be always available to the ap...

Страница 1079: ...le identifiers All bits of the incoming identifier must match the bits specified in the filter registers Filter bank scale and mode configuration The filter banks are configured by means of the corres...

Страница 1080: ...count the activation state of the filter banks In addition two independent numbering schemes are used one for each FIFO Refer to Figure 343 for an example One 32 Bit Filter Identifier Mask Two 16 Bit...

Страница 1081: ...f equal scale priority is given to the Identifier List mode over the Identifier Mask mode For filters of equal scale and mode priority is given by the filter number the lower the number the higher the...

Страница 1082: ...discarded by hardware without disturbing the software 32 7 5 Message storage The interface between the software and the hardware for the CAN messages is implemented by means of mailboxes A mailbox con...

Страница 1083: ...age available The filter match index is stored in the MFMI field of the CAN_RDTxR register The 16 bit time stamp value is stored in the TIME 15 0 field of CAN_RDTxR Figure 345 CAN error state diagram...

Страница 1084: ...the recovering sequence automatically after it has entered Bus Off state If ABOM is cleared the software must initiate the recovering sequence by requesting bxCAN to enter and to leave initialization...

Страница 1085: ...s moved earlier As a safeguard against programming errors the configuration of the Bit Timing Register CAN_BTR is only possible while the device is in Standby mode Note For a detailed description of t...

Страница 1086: ...ame Inter Frame Space Inter Frame Space or Overload Frame Inter Frame Space Inter Frame Space or Overload Frame Notes 0 N 8 SOF Start Of Frame ID Identifier RTR Remote Transmission Request IDE Identif...

Страница 1087: ...ition FOVR0 bit in the CAN_RF0R register set The FIFO 1 interrupt can be generated by the following events Reception of a new message FMP1 bits in the CAN_RF1R register are not 00 FIFO1 full condition...

Страница 1088: ...ver the modification of the filter configuration scale mode and FIFO assignment in CAN_FMxR CAN_FSxR and CAN_FFAR registers can only be done when the filter initialization mode is set FINIT 1 in the C...

Страница 1089: ...ion The SLEEP bit of the CAN_MCR register and the SLAK bit of the CAN_MSR register are cleared by hardware Bit 4 NART No automatic retransmission 0 The CAN hardware will automatically retransmit the m...

Страница 1090: ...Reserved SLAKI WKUI ERRI SLAK INAK r r r r rc_w1 rc_w1 rc_w1 r r Bits 31 12 Reserved must be kept at reset value Bit 11 RX CAN Rx signal Monitors the actual value of the CAN_RX Pin Bit 10 SAMP Last sa...

Страница 1091: ...t acknowledges the initialization request from the software set INRQ bit in CAN_MCR register This bit is cleared by hardware when the CAN hardware has left the initialization mode to be synchronized o...

Страница 1092: ...ssfully Please refer to Figure 340 Bit 16 RQCP2 Request completed mailbox2 Set by hardware when the last request transmit or abort has been performed Cleared by software writing a 1 or by hardware on...

Страница 1093: ...et by hardware when the last request transmit or abort has been performed Cleared by software writing a 1 or by hardware on transmission request TXRQ0 set in CAN_TI0R register Clearing this bit clears...

Страница 1094: ...Setting this bit when the FIFO is empty has no effect If at least two messages are pending in the FIFO the software has to release the output mailbox to access the next message Cleared by hardware whe...

Страница 1095: ...2 0 is set by hardware on error detection Bit 10 BOFIE Bus off interrupt enable 0 ERRI bit will not be set when BOFF is set 1 ERRI bit will be set when BOFF is set Bit 9 EPVIE Error passive interrupt...

Страница 1096: ...se of an error during reception this counter is incremented by 1 or by 8 depending on the error condition as defined by the CAN standard After every successful reception the counter is decremented by...

Страница 1097: ...ning limit has been reached Receive Error Counter or Transmit Error Counter 96 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 SILM LBKM Reserved SJW 1 0 Res TS2 2 0 TS1 3 0 rw rw rw rw rw rw rw rw rw...

Страница 1098: ...x allows access to a 3 level depth FIFO the access being offered only to the oldest received message in the FIFO Each mailbox consist of 4 registers Figure 349 RX and TX mailboxes Bits 19 16 TS1 3 0 T...

Страница 1099: ...10 9 8 7 6 5 4 3 2 1 0 EXID 12 0 IDE RTR TXRQ rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw Bits 31 21 STID 10 0 EXID 28 18 Standard identifier or extended identifier The standard identifier or the...

Страница 1100: ...s 15 9 Reserved must be kept at reset value Bit 8 TGT Transmit global time This bit is active only when the hardware is in the Time Trigger Communication mode TTCM bit of the CAN_MCR register is set 0...

Страница 1101: ...w Bits 31 24 DATA3 7 0 Data byte 3 Data byte 3 of the message Bits 23 16 DATA2 7 0 Data byte 2 Data byte 2 of the message Bits 15 8 DATA1 7 0 Data byte 1 Data byte 1 of the message Bits 7 0 DATA0 7 0...

Страница 1102: ...4 3 2 1 0 EXID 12 0 IDE RTR Res r r r r r r r r r r r r r r r Bits 31 21 STID 10 0 EXID 28 18 Standard identifier or extended identifier The standard identifier or the MSBs of the extended identifier...

Страница 1103: ...r r r r r r r r r r Bits 31 16 TIME 15 0 Message time stamp This field contains the 16 bit timer value captured at the SOF detection Bits 15 8 FMI 7 0 Filter match index This register contains the in...

Страница 1104: ...DATA1 7 0 DATA0 7 0 r r r r r r r r r r r r r r r r Bits 31 24 DATA3 7 0 Data Byte 3 Data byte 3 of the message Bits 23 16 DATA2 7 0 Data Byte 2 Data byte 2 of the message Bits 15 8 DATA1 7 0 Data By...

Страница 1105: ...N2SB 5 0 Reserved FINIT rw rw rw rw rw rw rw Bits 31 14 Reserved must be kept at reset value Bits 13 8 CAN2SB 5 0 CAN2 start bank These bits are set and cleared by software They define the start bank...

Страница 1106: ...w rw rw rw rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 FBM15 FBM14 FBM13 FBM12 FBM11 FBM10 FBM9 FBM8 FBM7 FBM6 FBM5 FBM4 FBM3 FBM2 FBM1 FBM0 rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw Bits 31 28...

Страница 1107: ...ts 31 28 Reserved must be kept at reset value Bits 27 0 FFAx Filter FIFO assignment for filter x The message passing through this filter will be stored in the specified FIFO 0 Filter assigned to FIFO...

Страница 1108: ...gister mapping addresses of the filter banks please refer to the Table 183 on page 1109 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 FB31 FB30 FB29 FB28 FB27 FB26 FB25 FB24 FB23 FB22 FB21 FB20 FB19...

Страница 1109: ...00C CAN_RF0R Reserved RFOM0 FOVR0 FULL0 Reserved FMP0 1 0 Reset value 0 0 0 0 0 0x010 CAN_RF1R Reserved RFOM1 FOVR1 FULL1 Reserved FMP1 1 0 Reset value 0 0 0 0 0 0x014 CAN_IER Reserved SLKIE WKUIE ERR...

Страница 1110: ...x x x x x x x x x x x x x x x x x x 0x1A8 CAN_TDL2R DATA3 7 0 DATA2 7 0 DATA1 7 0 DATA0 7 0 Reset value x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x 0x1AC CAN_TDH2R DATA7 7 0 DATA6...

Страница 1111: ...0 0 0x208 Reserved 0x20C CAN_FS1R Reserved FSC 27 0 Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0x210 Reserved 0x214 CAN_FFA1R Reserved FFA 27 0 Reset value 0 0 0 0 0 0 0 0 0...

Страница 1112: ...x x 0x318 CAN_F27R1 FB 31 0 Reset value x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x 0x31C CAN_F27R2 FB 31 0 Reset value x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x...

Страница 1113: ...e flexible peripheral to meet the needs of various applications and customers It supports two industry standard interfaces to the external physical layer PHY the default media independent interface MI...

Страница 1114: ...optional for multicast and unicast DA addresses Option to pass all multicast addressed frames Promiscuous mode support to pass all frames without any filtering for network monitoring Passes all incomi...

Страница 1115: ...burst fixed or indefinite burst in the AHB Master interface Option to select address aligned bursts from AHB master port Optimization for packet oriented DMA transfers with frame delimiters Byte alig...

Страница 1116: ...UP ETH_MII_CRS PA1 ETH_MII _RX_CLK ETH_RMII _REF_CLK PA2 ETH _MDIO PA3 ETH _MII_COL PA7 ETH_MII _RX_DV ETH_RMII _CRS_DV PB0 ETH _MII_RXD2 PB1 ETH _MII_RXD3 PB5 ETH _PPS_OUT PB8 ETH _MII_TXD3 PB10 ETH_...

Страница 1117: ...mode and features for the MAC and the DMA controller Note The AHB clock frequency must be at least 25 MHz when the Ethernet is used Figure 350 ETH block diagram 1 For AHB connections please refer to...

Страница 1118: ...d by a 01 pattern to verify transitions on the line from the default logic one state to zero and back to one Operation defines the type of transaction read or write in progress PADDR the PHY address i...

Страница 1119: ...gister or the MII Data Register during this period are ignored the Busy bit is high and the transaction is completed without any error After the Write operation has completed the SMI indicates this by...

Страница 1120: ...to set the clock ranges 33 4 2 Media independent interface MII The media independent interface MII defines the interconnection between the MAC sublayer and the PHY for data transfer at 10 Mbit s and 1...

Страница 1121: ...e transmit and receive media are idle The PHY must ensure that the MII_CS signal remains asserted throughout the duration of a collision condition This signal is not required to transition synchronous...

Страница 1122: ...with an external 25 MHz as shown in Figure 355 Instead of using an external 25 MHz quartz to provide this clock the STM32F4xxmicrocontroller can output this signal on its MCO pin In this case the PLL...

Страница 1123: ...edicated to reduce the pin count to 7 pins a 62 5 decrease in pin count The RMII is instantiated between the MAC and the PHY This helps translation of the MAC s MII into the RMII The RMII block has th...

Страница 1124: ...scheme required to support both the MII and RMII as well as 10 and 100 Mbit s operations is described in Figure 358 Figure 358 Clock scheme 1 The MII RMII selection is controlled through bit 23 MII_RM...

Страница 1125: ...encapsulation transmit and receive Framing frame boundary delimitation frame synchronization Addressing handling of source and destination addresses Error detection Media access management Medium allo...

Страница 1126: ...ast addresses this bit is also 1 Each byte of each address field must be transmitted least significant bit first The address designation is based on the following types Individual address this is the...

Страница 1127: ...y or may not be passed by the MAC sublayer Data and PAD fields n byte data field Full data transparency is provided it means that any arbitrary sequence of byte values may appear in the data field The...

Страница 1128: ...ra bits The CRC value computed on the incoming frame does not match the included FCS Preamble SFD Destination address Source address MAC client length type MAC client data PAD Frame check sequence 7 b...

Страница 1129: ...red and the new frame is considered as the continuation of the previous frame There are two modes of operation for popping data towards the MAC core In Threshold mode as soon as the number of bytes in...

Страница 1130: ...the deferral mechanism for flow control back pressure in Half duplex mode When the application requests to stop receiving frames the MAC sends a JAM pattern of 32 bytes whenever it senses the recepti...

Страница 1131: ...ime in the generated frame is the programmed pause time value in ETH_MACFCR If the receive FIFO remains full at a configurable number of slot times PLT bits in ETH_MACFCR before this Pause time runs o...

Страница 1132: ...IFO from the application DMA during the Flush operation Transfer transmit status words are transferred to the application for the number of frames that is flushed including partial frames Frames that...

Страница 1133: ...tects an IPv4 datagram when the Ethernet frame s Type field has the value 0x0800 and the IP datagram s Version field has the value 0x4 The input frame s checksum field is ignored during calculation an...

Страница 1134: ...DP or ICMPv6 pseudo header data are included into the checksum calculation and the checksum field is overwritten with the final calculated value Note that for ICMP over IPv4 packets the checksum field...

Страница 1135: ...roller 1232 Figure 362 Transmission bit order MII RMII transmit timing diagrams Figure 363 Transmission with no collision D0 D1 D2 D3 LSB MII_TXD 3 0 MSB D0 D1 LSB MSB RMII_TXD 1 0 Bibit stream Nibble...

Страница 1136: ...C in the ETH_DMAOMR register so that the DMA can initiate pre configured burst transfers towards the AHB interface In the default Cut through mode when 64 bytes configured with the RTC bits in the ETH...

Страница 1137: ...o CRC pad stripping option the MAC sends the data of the frame to RxFIFO up to the count specified in the length type field then starts dropping bytes including the FCS field If the Length Type field...

Страница 1138: ...ction In this configuration the core does not append any payload checksum bytes to the received Ethernet frames As mentioned in RDES0 Receive descriptor Word0 on page 1173 the meaning of certain regis...

Страница 1139: ...If the received control frame matches neither the type field 0x8808 the opcode 0x00001 nor the byte length 64 bytes or if there is a CRC error the MAC does not generate a Pause In the case of a pause...

Страница 1140: ...layer should be aware of the length of the frames received from the ingress port in order to transfer the frame to the egress port The MAC core provides the frame length of each received frame inside...

Страница 1141: ...core as a result of various events The ETH_MACSR register describes the events that can cause an interrupt from the MAC core You can prevent each event from asserting the interrupt by setting the cor...

Страница 1142: ...ected HU bit in the Frame filter register is reset the MAC compares all 48 bits of the received unicast address with the programmed MAC address for any match Default MacAddr0 is always enabled other a...

Страница 1143: ...lied to the received frame Broadcast address filter The MAC does not filter any broadcast frames in the default mode However if the MAC is programmed to reject all broadcast frames by setting the BFD...

Страница 1144: ...X Fail on hash filter match 0 1 1 0 X X X Pass on hash or perfect Group filter match 0 1 1 1 X X X Fail on hash or perfect Group filter match Multicast 1 X X X X X X Pass all frames X X X X X 1 X Pas...

Страница 1145: ...ers and lists the addresses of each of the statistics counters This address is used for read write accesses to the desired transmit receive counter The Receive MMC counters are updated for frames that...

Страница 1146: ...ote wakeup frame enable and Magic Packet enable These enable bits WFE and MPE are in the ETH_MACPMTCSR register and are programmed by the application When the power down mode is enabled in the PMT the...

Страница 1147: ...r block Remote wakeup frame detection When the MAC is in sleep mode and the remote wakeup bit is enabled in the ETH_MACPMTCSR register normal operation is resumed after receiving a remote wakeup frame...

Страница 1148: ...F FFFF pattern is scanned for again in the incoming frame The 16 repetitions can be anywhere in the frame but must be preceded by the synchronization stream 0xFFFF FFFF FFFF The device also accepts a...

Страница 1149: ...mode 11 On receiving a valid wakeup frame the Ethernet peripheral exits the power down mode 12 Read the ETH_MACPMTCSR to clear the power management event flag enable the MAC transmitter state machine...

Страница 1150: ...to synchronize its local timing reference to the master s timing reference Most of the protocol implementation occurs in the software above the UDP layer As described above however hardware support i...

Страница 1151: ...the IEEE 1588 time stamping feature is enabled the Ethernet MAC captures the time stamp of all frames received on the MII The MAC provides the time stamp as soon as the frame reception is complete Ca...

Страница 1152: ...to 67 MHz for example the addend register must be set to 0xBF0 B7672 When the clock drift is zero the default addend value of 0xC1F0 7C1F 232 1 32 should be programmed In Figure 373 the constant value...

Страница 1153: ...rithm is self correcting if for any reason the slave clock is initially set to a value from the master that is incorrect the algorithm corrects it at the cost of more Sync cycles Programming steps for...

Страница 1154: ...ed target time in the Target time high and low registers Unmask the Time stamp interrupt by clearing bit 9 in the ETH_MACIMR register 5 Set Time stamp control register bit 4 TSARU 6 When this trigger...

Страница 1155: ...ry into the Tx FIFO while the receive engine transfers data from the Rx FIFO into system memory The controller utilizes descriptors to efficiently move data from source to destination with minimum CPU...

Страница 1156: ...egisters providing the DMA with the start address of each list 4 Write to MAC Registers 1 2 and 3 to choose the desired filtering options 5 Write to the MAC ETH_MACCR register to configure and enable...

Страница 1157: ...less than or equal to the size of the configured PBL Thus all subsequent beats start at an address that is aligned to the configured PBL The DMA can only align the address for beats up to size 16 for...

Страница 1158: ...00 and 0x1001 The actual frame is written from location 0x1002 Thus the actual useful space in this buffer is 1022 bytes even though the buffer size is programmed as 1024 bytes due to the start addres...

Страница 1159: ...ion is complete if IEEE 1588 time stamping was enabled for the frame as indicated in the transmit status the time stamp value is written to the transmit descriptor TDES2 and TDES3 that contains the en...

Страница 1160: ...he transmit descriptor list for the second frame If the second frame is valid the transmit process transfers this frame before writing the first frame s status information In OSF mode the Run state tr...

Страница 1161: ...mp to TDES2 and TDES3 if such time stamp was captured as indicated by a status bit The DMA then writes the status with a cleared OWN bit to the corresponding TDES0 thus closing the descriptor If time...

Страница 1162: ...are transferred from the memory buffer to the Transmit FIFO Concurrently if the last descriptor TDES0 29 of the current frame is cleared the transmit process attempts to acquire the next descriptor Th...

Страница 1163: ...o underflow is detected The appropriate Transmit Descriptor 0 TDES0 bit is set If the second condition occurs both the Abnormal Interrupt Summary in ETH_DMASR register 15 and Transmit Underflow bits i...

Страница 1164: ...he buffer contains the last segment of the frame Bit 28 FS First segment When set this bit indicates that the buffer contains the first segment of a frame Bit 27 DC Disable CRC When this bit is set th...

Страница 1165: ...the IPv4 packet against the number of header bytes received from the application and indicates an error status if there is a mismatch For IPv6 frames a header error is reported if the main header leng...

Страница 1166: ...ission of the frame is aborted Bit 7 VF VLAN frame When set this bit indicates that the transmitted frame was a VLAN type frame Bits 6 3 CC Collision count This 4 bit counter value indicates the numbe...

Страница 1167: ...0 TBAP1 TBAP TTSL rw Bits 31 0 TBAP1 Transmit buffer 1 address pointer Transmit frame time stamp low These bits have two different functions they indicate to the DMA the location of data in memory and...

Страница 1168: ...0 TBAP2 Transmit buffer 2 address pointer Next descriptor address Transmit frame time stamp high These bits have two different functions they indicate to the DMA the location of data in memory and aft...

Страница 1169: ...ER BYTE COUNT UFFER ADDRESS UFFER ADDRESS OR EXT DESCRIPTOR ADDRESS 4 3 4 3 4 3 AI B 4 4 3 4 4 3 3 4 3 4 3 4 3 4 3 2ESERVED 2ESERVED 4IME STAMP LOW 4IME STAMP HIGH 31 30 29 28 27 26 25 24 23 22 21 20...

Страница 1170: ...s not disabled then proceeds to step 8 If the DMA owns the next descriptor but the current frame transfer is not complete the DMA closes the current descriptor as intermediate and returns to step 4 7...

Страница 1171: ...if time stamping is not enabled RDES2 and RDES3 remain unchanged Figure 381 Receive DMA operation Re Fetch next descriptor AHB error No Own bit set Yes Yes Stop RxDMA Start RxDMA Start AHB error No R...

Страница 1172: ...A sets the first descriptor RDES0 9 after the DMA AHB Interface becomes ready to receive a data transfer if DMA is not fetching transmit data from the memory to delimit the frame The descriptors are r...

Страница 1173: ...31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 OWN AFM FL ES DE SAF LE OE VLAN FS LS IPHCE TSV LCO FT RWT RE DE CE PCE ESA rw Bit 31 OWN Own bit When set this bi...

Страница 1174: ...erflow Bit 10 VLAN VLAN tag When set this bit indicates that the frame pointed to by this descriptor is a VLAN frame tagged by the MAC core Bit 9 FS First descriptor When set this bit indicates that t...

Страница 1175: ...2 DE Dribble bit error When set this bit indicates that the received frame has a non integer multiple of bytes odd nibbles This bit is valid only in MII mode Bit 1 CE CRC error When set this bit indi...

Страница 1176: ...29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 DIC RBS2 RBS2 RER RCH Reserved RBS rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw...

Страница 1177: ...rw rw Bits 31 0 RBAP1 RTSL Receive buffer 1 address pointer Receive frame time stamp low These bits take on two different functions the application uses them to indicate to the DMA where to store the...

Страница 1178: ...fer 2 address pointer next descriptor address Receive frame time stamp high These bits take on two different functions the application uses them to indicate to the DMA the location of where to store t...

Страница 1179: ...5 RDES 6 Extended Status 31 0 Reserved Time stamp low 31 0 Time stamp high 31 0 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved PV PFT PMT IPV6PR IPV4PR...

Страница 1180: ...d packet is an IPv6 packet Bit 6 IPV4PR IPv4 packet received When set this bit indicates that the received packet is an IPv4 packet Bit 5 IPCB IP checksum bypassed When set this bit indicates that the...

Страница 1181: ...The interrupt is not generated again unless a new interrupting event occurs after the driver has cleared the appropriate bit in the ETH_DMASR register For example the controller generates a Receive in...

Страница 1182: ...EXTI Line19 interrupt with detection on rising edge is also enabled both interrupts are generated A watchdog timer see ETH_DMARSWTR register is given for flexible control of the RS bit ETH_DMASR regis...

Страница 1183: ...Reset value 0x0000 8000 The MAC configuration register is the operation mode register of the MAC It establishes receive and transmit operating modes 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15...

Страница 1184: ...the MAC receives all packets that are given by the PHY while transmitting This bit is not applicable if the MAC is operating in Full duplex mode Bit 12 LM Loopback mode When this bit is set the MAC op...

Страница 1185: ...e deferral error bit set in the transmit frame status when the transmit state machine is deferred for more than 24 288 bit times in 10 100 Mbit s mode Deferral begins when the transmitter is ready to...

Страница 1186: ...he application only those frames that have passed the SA DA address filter Bits 30 11 Reserved must be kept at reset value Bit 10 HPF Hash or perfect filter When this bit is set and if the HM or HU bi...

Страница 1187: ...n even if they fail the address filter 11 MAC forwards control frames that pass the address filter Bit 5 BFD Broadcast frames disable When this bit is set the address filters filter all incoming broad...

Страница 1188: ...he Hash table high register contains the higher 32 bits of the multicast Hash table Ethernet MAC hash table low register ETH_MACHTLR Address offset 0x000C Reset value 0x0000 0000 The Hash table low re...

Страница 1189: ...110 111 Reserved Bit 1 MW MII write When set this bit tells the PHY that this will be a Write operation using the MII Data register If this bit is not set this will be a Read operation placing the da...

Страница 1190: ...s in the destination clock domain Bits 15 8 Reserved must be kept at reset value Bit 7 ZQPD Zero quanta pause disable When set this bit disables the automatic generation of Zero quanta pause control f...

Страница 1191: ...frames In Half duplex mode when this bit is set the MAC enables the back pressure operation When this bit is reset the back pressure feature is disabled Bit 0 FCB BPA Flow control busy back pressure...

Страница 1192: ...are compared with the corresponding field in the received VLAN tagged frame When this bit is reset all 16 bits of the received VLAN frame s fifteenth and sixteenth bytes are used for comparison Bits...

Страница 1193: ...eset value Bit 6 WFR Wakeup frame received When set this bit indicates the power management event was generated due to reception of a wakeup frame This bit is cleared by a read into this register Bit...

Страница 1194: ...smission Bit 23 Reserved must be kept at reset value Bit 22 TFWA Tx FIFO write active When high it indicates that the TxFIFO write controller is active and transferring data to the TxFIFO Bits 21 20 T...

Страница 1195: ...ate 01 Reading frame data 10 Reading frame status or time stamp 11 Flushing the frame data and status Bit 4 RFWRA Rx FIFO write controller active When high it indicates that the Rx FIFO write controll...

Страница 1196: ...transmit status This bit is set high whenever an interrupt is generated in the ETH_MMCTIR Register This bit is cleared when all the bits in this interrupt register ETH_MMCTIR are cleared Bit 5 MMCRS...

Страница 1197: ...er 47 0 is compared with 0x6655 4433 2211 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved TSTIM Reserved PMTIM Reserved rw rw Bits 15 10 Reserved must be kept at reset value Bit 9 TSTIM Time stamp trig...

Страница 1198: ...rw rw rw rw Bits 31 0 MACA0L MAC address0 low 31 0 This field contains the lower 32 bits of the 6 byte MAC address0 This is used by the MAC for filtering for received frames and for inserting the MAC...

Страница 1199: ...the MAC address1 registers Each bit controls the masking of the bytes as follows Bit 29 ETH_MACA1HR 15 8 Bit 28 ETH_MACA1HR 7 0 Bit 27 ETH_MACA1LR 31 24 Bit 24 ETH_MACA1LR 7 0 Bits 23 16 Reserved mus...

Страница 1200: ...ntrol These bits are mask control bits for comparison of each of the MAC address2 bytes When set high the MAC core does not compare the corresponding byte of received DA SA with the contents of the MA...

Страница 1201: ...or comparison with the SA fields of the received frame When this bit is cleared the MAC address 3 47 0 is used for comparison with the DA fields of the received frame Bits 29 24 MBC Mask byte control...

Страница 1202: ...half 16 When MCFHP is high and bit4 is set all MMC counters get preset to almost full value All frame counters get preset to 0xFFFF_FFF0 full 16 Bit 4 MCP MMC counter preset When set all counters will...

Страница 1203: ...6 5 4 3 2 1 0 Reserved RGUFS Reserved RFAES RFCES Reserved rc_r rc_r rc_r Bits 31 18 Reserved must be kept at reset value Bit 17 RGUFS Received Good Unicast Frames Status This bit is set when the rece...

Страница 1204: ...tted good frames after a single collision counter reaches half the maximum value Bits 13 0 Reserved must be kept at reset value 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7...

Страница 1205: ...M Reserved rw rw rw Bits 31 22 Reserved must be kept at reset value Bit 21 TGFM Transmitted good frames mask Setting this bit masks the interrupt when the transmitted good frames counter reaches half...

Страница 1206: ...4 Reset value 0x0000 0000 This register contains the number of frames received with CRC error 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 TGFMSCC r r r r r r...

Страница 1207: ...ontrol register ETH_PTPTSCR Address offset 0x0700 Reset value 0x0000 00002000 This register controls the time stamp generation and update logic 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13...

Страница 1208: ...is taken for IPv6 frames Bit 11 TSSPTPOEFE Time stamp snapshot for PTP over ethernet frames enable When this bit is set the time stamp snapshot is taken for frames which have PTP messages in Ethernet...

Страница 1209: ...Time stamp high update and Time stamp low update registers This bit must be read as zero before you can set it When initialization is complete this bit is cleared Bit 1 TSFCU Time stamp fine or coars...

Страница 1210: ...ains the seconds system time value The Time stamp high register along with Time stamp low register indicates the current value of the system time maintained by the MAC Though it is updated on a contin...

Страница 1211: ...SSTI or TSSTU bits in the Time stamp control register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 STPNS STSS r r r r r r r r r r r r r r r r r r r r r r r r r...

Страница 1212: ...rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw Bit 31 TSUPNS Time stamp update positive or negative sign This bit indicates positive or negative time value When s...

Страница 1213: ...et 0x0728 Reset value 0x0000 0000 This register contains the time stamp status register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 TTSH rw rw rw rw rw rw rw...

Страница 1214: ...ed PPSFREQ ro ro Bits 31 4 Reserved must be kept at reset value Bits 3 0 PPSFREQ PPS frequency selection The PPS output frequency is set to 2PPSFREQ Hz 0000 1 Hz with a pulse width of 125 ms for binar...

Страница 1215: ...urst accessing the data buffer s start address is not aligned but subsequent bursts are aligned to the address Bit 24 FPM 4xPBL mode When set high this bit multiplies the PBL value programmed bits 22...

Страница 1216: ...lue is applicable for TxDMA transactions only The PBL values have the following limitations The maximum number of beats PBL possible is limited by the size of the Tx FIFO and Rx FIFO The FIFO has a co...

Страница 1217: ...bits low Writing to the ETH_DMARDLAR register is permitted only when reception is stopped When stopped the ETH_DMARDLAR register must be written to before the receive Start command is given 31 30 29...

Страница 1218: ...gister bits are not cleared when read Writing 1 to unreserved bits in ETH_DMASR register 16 0 clears them and writing 0 has no effect Each field bits 16 0 can be masked by masking the appropriate bit...

Страница 1219: ...rror response on the AHB interface Valid only with the fatal bus error bit ETH_DMASR register 13 set This field does not generate an interrupt Bit 231 Error during data transfer by TxDMA 0 Error durin...

Страница 1220: ...sticky bit and it must be cleared each time a corresponding bit that causes AIS to be set is cleared Bit 14 ERS Early receive status This bit indicates that the DMA had filled the first data buffer o...

Страница 1221: ...ES0 11 Bit 3 TJTS Transmit jabber timeout status This bit indicates that the transmit jabber timer expired meaning that the transmitter had been excessively active The transmission process is aborted...

Страница 1222: ...process suspended on page 1172 Bits 23 22 Reserved must be kept at reset value Bit 21 TSF Transmit store and forward When this bit is set transmission starts when a full frame resides in the Transmit...

Страница 1223: ...ts 12 8 Reserved must be kept at reset value Bit 7 FEF Forward error frames When this bit is set all frames except runt error frames are forwarded to the DMA When this bit is cleared the Rx FIFO drops...

Страница 1224: ...register or the position retained when the receive process was previously stopped If no descriptor is owned by the DMA reception is suspended and the receive buffer unavailable bit ETH_DMASR 7 is set...

Страница 1225: ...en this bit is set an abnormal interrupt is enabled When this bit is cleared an abnormal interrupt is disabled This bit enables the following bits ETH_DMASR 1 Transmit process stopped ETH_DMASR 3 Tran...

Страница 1226: ...leared the receive interrupt is disabled Bit 5 TUIE Underflow interrupt enable When this bit is set with the abnormal interrupt summary enable bit ETH_DMAIER register 15 the transmit underflow interru...

Страница 1227: ..._ r rc_ r rc_ r rc_ r rc_ r rc_ r rc_ r rc_ r rc_ r rc_ r rc_ r rc_ r Bits 31 29 Reserved must be kept at reset value Bit 28 OFOC Overflow bit for FIFO overflow counter Bits 27 17 MFA Missed frames by...

Страница 1228: ...ost transmit buffer address register points to the current transmit buffer address being read by the DMA 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 HTDAP r r...

Страница 1229: ...6 5 4 3 2 1 0 0x00 ETH_MACCR Reserved CSTF eserved WD JD Reserved IFG CSD Reserved FES ROD LM DM IPCO RD Reserved APCS BL DC TE RE Reserved Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0x04 ETH_...

Страница 1230: ...0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0x4C ETH_MACA1LR MACA1L Reset value 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0x50 ETH_MACA2HR AE SA MBC Reserved MACA2H Reset value 0 0 0 0...

Страница 1231: ...TSSIPV6FE TSSPTPOEFE TSPTPPSV2E TSSSR TSSARFE Reserved TTSARU TSITE TSSTU TSSTI TSFCU TSE Reset value 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0x704 ETH_PTPSSIR Reserved STSSI Reset value 0 0 0 0 0 0 0 0 0x7...

Страница 1232: ...t value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0x1018 ETH_DMAOMR Reserved DTCEFD RSF DFRF Reserved TSF FTF Reserve d TTC ST Reserved FEF FUGF Reserved RTC OSF SR Reserved Reset value 0...

Страница 1233: ...pports both device and host functions and is fully compliant with the On The Go Supplement to the USB 2 0 Specification It can also be configured as a host only or device only controller fully complia...

Страница 1234: ...Configurable end of frame interrupt It includes power saving features such as system stop during USB Suspend switch off of clock domains internal to the digital core PHY and DFIFO power management It...

Страница 1235: ...ulk Interrupt or Isochronous transfers Management of a shared Rx FIFO and a Tx OUT FIFO for efficient usage of the USB data RAM Management of up to 4 dedicated Tx IN FIFOs one for each active IN EP to...

Страница 1236: ...ll speed subset of the UTMI Bus UTMIFS It provides the physical support to USB connectivity The full speed OTG PHY includes the following components FS LS transceiver module used by both host and devi...

Страница 1237: ...is connected with a grounded ID the OTG_FS issues an ID line status change interrupt CIDSCHG bit in OTG_FS_GINTSTS for host software initialization and automatically switches to the host role In this...

Страница 1238: ...tches the OTG_FS to its peripheral role B device If the ID line is present functional and connected to the B side of the USB cable and the HNP capable bit in the Global USB Configuration register HNPC...

Страница 1239: ...l full speed device connection to the host and generates the session request interrupt SRQINT bit in OTG_FS_GINTSTS to notify the powered state The VBUS input also ensures that valid VBUS levels are s...

Страница 1240: ...ended state The suspended state may optionally be exited by the device itself In this case the application sets the remote wakeup signaling bit in the device control register RWUSIG bit in OTG_FS_DCTL...

Страница 1241: ...gh the device endpoint x IN OUT control register DIEPCTLx DOEPCTLx Endpoint enable disable Endpoint activate in current configuration Program USB transfer type isochronous bulk interrupt Program suppo...

Страница 1242: ...point was not yet enabled Babble error condition has been detected Endpoint disable by application is effective Endpoint NAK by application is effective isochronous in only More than 3 back to back se...

Страница 1243: ...1 SRP capable host SRP support is available through the SRP capable bit in the global USB configuration register SRPCAP bit in OTG_FS_GUSBCFG With the SRP feature enabled the host can save power by sw...

Страница 1244: ...in OTG_FS_HPRT Host detection of peripheral a disconnection The peripheral disconnection event triggers the disconnect detected interrupt DISCINT bit in OTG_FS_GINTSTS Host enumeration After detectin...

Страница 1245: ...er completed and channel halted interrupts Each host channel can be configured to support in out and any type of periodic nonperiodic transaction Each host channel makes us of proper control HCCHARx t...

Страница 1246: ...r false EOP Babble error fraMe overrun dAta toggle error 34 6 4 Host scheduler The host core features a built in hardware scheduler which is able to autonomously re order and manage the USB transactio...

Страница 1247: ...riodic nonperiodic request queue by reading the PTXQSAV bits in the OTG_FS_HNPTXSTS register or NPTQXSAV bits in the OTG_FS_HNPTXSTS register 34 7 SOF trigger Figure 390 SOF connectivity The OTG FS co...

Страница 1248: ...feature and the timer can be triggered by the SOF pulse The TIM2 connection is enabled through the ITR1_RMP bits of the TIM2 option register TIM2_OR The end of periodic frame interrupt GINTSTS EOPF is...

Страница 1249: ...rastically reduce the overall power consumption by a complete shut down of all the clock sources in the system USB System Stop is activated by first setting the Stop PHY clock bit and then configuring...

Страница 1250: ...FIFO that receives the data directed to all OUT endpoints Received packets are stacked back to back until free space is available in the Rx FIFO The status of the received packet which contains the O...

Страница 1251: ...IEPTXFx for IN endpoint x 34 12 Host FIFO architecture Figure 393 Host mode FIFO address mapping and AHB FIFO access mapping 34 12 1 Host Rx FIFO The host uses one receiver FIFO for all periodic and n...

Страница 1252: ...iodic nonperiodic transactions in the OUT direction share the same RAM buffer shared FIFOs The OTG FS core can fill in the periodic nonperiodic transmit FIFO up to the limit for any sequence of OUT to...

Страница 1253: ...t Packet Size 4 1 spaces are recommended so that when the previous packet is being transferred to the CPU the USB can receive the subsequent packet Along with the last packet in the host channel trans...

Страница 1254: ...with the data coming from the USB As the OTG_FS core is able to fill in the 1 25 Kbyte RAM buffer very efficiently and as 1 25 Kbyte of transmit receive data is more than enough to cover a full speed...

Страница 1255: ...ied as follows Core global registers Host mode registers Host global registers 31 30 29 28 27 26 25 24 23 20 19 18 17 10 9 8 7 3 2 1 0 AND OR Interrupt Global interrupt mask Bit 0 AHB configuration re...

Страница 1256: ...host port control and status registers can be accessed in both host and device modes When the OTG_FS controller is operating in one mode either device or host the application must not access registers...

Страница 1257: ...nnel 1 FIFO 4 Kbyte 3000h Device EP x 1 1 Host channel x 1 1 FIFO 4 Kbyte Device EP x 1 Host channel x 1 FIFO 4 Kbyte Reserved DFIFO push pop to this region 2 0000h 3 FFFFh Direct access to data FIFO...

Страница 1258: ...core ID register OTG_FS_CID on page 1281 OTG_FS_HPTXFSIZ 0x100 OTG_FS Host periodic transmit FIFO size register OTG_FS_HPTXFSIZ on page 1282 OTG_FS_DIEPTXFx 0x104 0x124 0x138 OTG_FS device IN endpoint...

Страница 1259: ...d status registers Acronym Offset address Register name OTG_FS_DCFG 0x800 OTG_FS device configuration register OTG_FS_DCFG on page 1293 OTG_FS_DCTL 0x804 OTG_FS device control register OTG_FS_DCTL on...

Страница 1260: ...size register OTG_FS_DIEPTSIZ0 on page 1310 OTG_FS_DTXFSTSx 0x918 OTG_FS device IN endpoint transmit FIFO status register OTG_FS_DTXFSTSx x 0 3 where x Endpoint_number on page 1313 OTG_FS_DIEPTSIZx 0...

Страница 1261: ...nt 0 Host IN Channel 0 DFIFO Read Access 0x1000 0x1FFC w r Device IN Endpoint 1 Host OUT Channel 1 DFIFO Write Access Device OUT Endpoint 1 Host IN Channel 1 DFIFO Read Access 0x2000 0x2FFC w r Device...

Страница 1262: ...ed must be kept at reset value Bit 19 BSVLD B session valid Indicates the device mode transceiver status 0 B session is not valid 1 B session is valid In OTG mode you can use this bit to determine if...

Страница 1263: ...negotiation success The core sets this bit when host negotiation is successful The core clears this bit when the HNP Request HNPRQ bit in this register is set 0 Host negotiation failure 1 Host negotia...

Страница 1264: ...out while waiting for the B device to connect Note Accessible in both device and host modes Bit 17 HNGDET Host negotiation detected The core sets this bit when it detects a host negotiation request o...

Страница 1265: ...errupt indicates that the Periodic TxFIFO is completely empty Note Only accessible in host mode Bit 7 TXFELVL TxFIFO empty level In device mode this bit indicates when IN endpoint Transmit FIFO empty...

Страница 1266: ...irrespective of the OTG_FS_ID input pin 0 Normal mode 1 Force device mode After setting the force bit the application must wait at least 25 ms before the change takes effect Note Accessible in both de...

Страница 1267: ...reset value Bits 2 0 TOCAL FS timeout calibration The number of PHY clocks that the application programs in this field is added to the full speed interpacket timeout duration in the core to account fo...

Страница 1268: ...ush in device mode 10000 Flush all the transmit FIFOs in device or host mode Note Accessible in both device and host modes Bit 5 TXFFLSH TxFIFO flush This bit selectively flushes a single or all trans...

Страница 1269: ...lears the interrupts and all the CSR register bits except for the following bits RSTPDMODL bit in OTG_FS_PCGCCTL GAYEHCLK bit in OTG_FS_PCGCCTL PWRCLMP bit in OTG_FS_PCGCCTL STPPCLK bit in OTG_FS_PCGC...

Страница 1270: ...SOF OTGINT MMIS CMOD rc_w1 r r r Res rc_w1 r r rc_w1 r r r r rc_w1 r rc_w1 r Bit 31 WKUPINT Resume remote wakeup detected interrupt In device mode this interrupt is asserted when a resume is detected...

Страница 1271: ...ster Bit 20 IISOIXFR Incomplete isochronous IN transfer The core sets this interrupt to indicate that there is at least one isochronous IN endpoint on which the transfer is not completed in the curren...

Страница 1272: ...NAK bit in the OTG_FS_DCTL register SGONAK bit in OTG_FS_DCTL set by the application has taken effect in the core This bit can be cleared by writing the Clear global OUT NAK bit in the OTG_FS_DCTL re...

Страница 1273: ...ent The application must read the OTG Interrupt Status OTG_FS_GOTGINT register to determine the exact event that caused this interrupt The application must clear the appropriate status bit in the OTG_...

Страница 1274: ...rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw Bit 31 WUIM Resume remote wakeup detected interrupt mask 0 Masked interrupt 1 Unmasked interrupt Note Accessible in both host and device modes Bit 30 SRQIM...

Страница 1275: ...accessible in device mode Bit 18 IEPINT IN endpoints interrupt mask 0 Masked interrupt 1 Unmasked interrupt Note Only accessible in device mode Bit 17 EPMISM Endpoint mismatch interrupt mask 0 Masked...

Страница 1276: ...interrupt 1 Unmasked interrupt Note Only accessible in device mode Bit 5 NPTXFEM Non periodic TxFIFO empty mask 0 Masked interrupt 1 Unmasked interrupt Note Only accessible in Host mode Bit 4 RXFLVLM...

Страница 1277: ...only pop the Receive Status FIFO when the Receive FIFO non empty bit of the Core interrupt register RXFLVL bit in OTG_FS_GINTSTS is asserted Host mode 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16...

Страница 1278: ...the received packet 0001 Global OUT NAK triggers an interrupt 0010 OUT data packet received 0011 OUT transfer completed triggers an interrupt 0100 SETUP transaction completed triggers an interrupt 011...

Страница 1279: ...8 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 NPTXFD TX0FD NPTXFSA TX0FSA r rw r rw Bits 31 16 NPTXFD Non periodic TxFIFO depth This value is in terms of 32 bit words Min...

Страница 1280: ...uest queue space available Indicates the amount of free space available in the non periodic transmit request queue This queue holds both IN and OUT requests in host mode Device mode has only IN reques...

Страница 1281: ...ications 0 VBUS sensing available by hardware 1 VBUS sensing not available by hardware Bit 20 SOFOUTEN SOF output enable 0 SOF pulse not available on PAD 1 SOF pulse available on PAD Bit 19 VBUSBSEN E...

Страница 1282: ...bit words Minimum value is 16 Bits 15 0 PTXSA Host periodic TxFIFO start address The power on reset value of this register is the sum of the largest Rx data FIFO depth and largest non periodic Tx data...

Страница 1283: ...21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved FSLSS FSLSPCS r rw rw Bits 31 3 Reserved must be kept at reset value Bit 2 FSLSS FS and LS only support The application uses this bit t...

Страница 1284: ...bit of the host port control and status register PENA bit in OTG_FS_HPRT has been set If no value is programmed the core calculates the value based on the PHY clock specified in the FS LS PHY Clock S...

Страница 1285: ...endpoint number Bits 26 25 Type 00 IN OUT 01 Zero length packet 11 Disable channel command Bit 24 Terminate last entry for the selected channel endpoint Bits 23 16 PTXQSAV Periodic transmit request q...

Страница 1286: ...through the host port interrupt bit of the core interrupt register HPRTINT bit in OTG_FS_GINTSTS On a Port Interrupt the application must read this register and clear the bit that caused the interrupt...

Страница 1287: ...e clearing the bit even though there is no maximum limit set by the USB standard Bit 7 PSUSP Port suspend The application sets this bit to put this port in Suspend mode The core only stops sending SOF...

Страница 1288: ...he core after a reset sequence and is disabled by an overcurrent condition a disconnect condition or by the application clearing this bit The application cannot set this bit by a register write It can...

Страница 1289: ...d Bit 29 ODDFRM Odd frame This field is set reset by the application to indicate that the OTG host must perform a transfer in an odd frame This field is applicable for only periodic isochronous and in...

Страница 1290: ..._GINTSTS registers Bit 15 EPDIR Endpoint direction Indicates whether the transaction is IN or OUT 0 OUT 1 IN Bits 14 11 EPNUM Endpoint number Indicates the endpoint number on the device serving as the...

Страница 1291: ...15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved DTERRM FRMORM BBERRM TXERRM NYET ACKM NAKM STALLM Reserved CHHM XFRCM rw rw rw rw rw rw rw rw rw rw Bits 31 11 Reserved must be kept at reset value Bit 1...

Страница 1292: ...pplication programs this field with the type of PID to use for the initial transaction The host maintains this field for the rest of the transfer 00 DATA0 01 DATA2 10 DATA1 11 MDATA non control SETUP...

Страница 1293: ...of the frame interval Bits 10 4 DAD Device address The application must program this field after every SetAddress control command Bit 3 Reserved must be kept at reset value Bit 2 NZLSOHSK Non zero len...

Страница 1294: ...this bit only after making sure that the Global OUT NAK effective bit in the Core interrupt register GONAKEFF bit in OTG_FS_GINTSTS is cleared Bit 8 CGINAK Clear global IN NAK A write to this field cl...

Страница 1295: ...d and the device does not receive signals on the USB The core stays in the disconnected state until the application clears this bit 0 Normal operation When this bit is cleared after a soft disconnect...

Страница 1296: ...ed speed Indicates the speed at which the OTG_FS controller has come up after speed detection through a chirp sequence 01 Reserved 10 Reserved 11 Full speed PHY clock is running at 48 MHz Others reser...

Страница 1297: ...reset value Bit 1 EPDM Endpoint disabled interrupt mask 0 Masked interrupt 1 Unmasked interrupt Bit 0 XFRCM Transfer completed interrupt mask 0 Masked interrupt 1 Unmasked interrupt 31 30 29 28 27 26...

Страница 1298: ...he OTG_FS_DAINTMSK register works with the Device endpoint interrupt register to interrupt the application when an event occurs on a device endpoint However the OTG_FS_DAINT register bit corresponding...

Страница 1299: ...21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved VBUSDT rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw Bits 31 16 Reserved must be kept at reset value Bits 15 0 VBUSDT Device VBUS di...

Страница 1300: ...point disabled Transfer completed Bit 30 EPDIS Endpoint disable The application sets this bit to stop transmitting data on an endpoint even before the transfer for that endpoint is complete The applic...

Страница 1301: ...esponds to SETUP data packets with an ACK handshake Bit 16 Reserved must be kept at reset value Bit 15 USBAEP USB active endpoint This bit is always set to 1 indicating that control endpoint 0 is alwa...

Страница 1302: ...The core can also set this bit for OUT endpoints on a Transfer completed interrupt or after a SETUP is received on the endpoint Bit 26 CNAK Clear NAK A write to this bit clears the NAK bit for the en...

Страница 1303: ...in which it intends to transmit receive isochronous data for this endpoint using the SEVNFRM and SODDFRM fields in this register 0 Even frame 1 Odd frame DPID Endpoint data PID Applies to interrupt b...

Страница 1304: ...its 29 28 Reserved must be kept at reset value Bit 27 SNAK Set NAK A write to this bit sets the NAK bit for the endpoint Using this bit the application can control the transmission of NAK handshakes o...

Страница 1305: ...ke Bit 16 Reserved must be kept at reset value Bit 15 USBAEP USB active endpoint This bit is always set to 1 indicating that a control endpoint 0 is always active in all configurations and interfaces...

Страница 1306: ...ng this bit the application can control the transmission of NAK handshakes on an endpoint The core can also set this bit for OUT endpoints on a Transfer Completed interrupt or after a SETUP is receive...

Страница 1307: ...his endpoint using the SEVNFRM and SODDFRM fields in this register 0 Even frame 1 Odd frame DPID Endpoint data PID Applies to interrupt bulk OUT endpoints only Contains the PID of the packet to be rec...

Страница 1308: ...ly empty status is determined by the TxFIFO Empty Level bit in the OTG_FS_GAHBCFG register TXFELVL bit in OTG_FS_GAHBCFG Bit 6 INEPNE IN endpoint NAK effective This bit can be cleared when the applica...

Страница 1309: ...rc_ w1 rc_ w1 Bits 31 7 Reserved must be kept at reset value Bit 6 B2BSTUP Back to back SETUP packets received Applies to control OUT endpoint only This bit indicates that the core has received more t...

Страница 1310: ...13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved PKTCNT Reserved XFRSIZ rw rw rw rw rw rw rw rw rw Bits 31 21 Reserved must be kept at reset value Bits 20 19 PKTCNT Packet count Indicates the total number of...

Страница 1311: ...PKTCNT Reserved XFRSIZ rw rw rw rw rw rw rw rw rw rw Bit 31 Reserved must be kept at reset value Bits 30 29 STUPCNT SETUP packet count This field specifies the number of back to back SETUP data packet...

Страница 1312: ...rw Bit 31 Reserved must be kept at reset value Bits 30 29 MCNT Multi count For periodic IN endpoints this field indicates the number of packets that must be transmitted per frame on the USB The core u...

Страница 1313: ...ister once the core has cleared the Endpoint enable bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved INEPTFSAV r r r r r r r r r r r r r r r r 31 16 R...

Страница 1314: ...the maximum packet size of the endpoint to be interrupted at the end of each packet The core decrements this field every time a packet is read from the RxFIFO and written to the external memory 31 30...

Страница 1315: ...0 0x010 OTG_FS_GRS TCTL AHBIDL Reserved TXFNUM RXFFLSH Reserved FCRST HSRST CSRST Reset value 1 0 0 0 0 0 0 0 0 0 0 0x014 OTG_FS_GIN TSTS WKUINT SRQINT DISCINT CIDSCHG Reserved PTXFE HCINT HPRTINT Re...

Страница 1316: ...0 0 0 0x100 OTG_FS_HPT XFSIZ PTXFSIZ PTXSA Reset value 0 0 0 0 0 1 1 1 0 1 1 0 1 0 0 0 0 0 0 1 0 0 0 0 0 0 1 0 0 1 0 0 0x104 OTG_FS_DIE PTXF1 INEPTXFD INEPTXSA Reset value 0 0 0 0 0 0 1 0 0 0 0 0 0 0...

Страница 1317: ...0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0x580 OTG_FS_HCC HAR4 CHENA CHDIS ODDFRM DAD MCN T EPTYP LSDEV Reserved EPDIR EPNUM MPSIZ Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0...

Страница 1318: ...value 0 0 0 0 0 0 0 0 0 0x50C OTG_FS_HCI NTMSK0 Reserved DTERRM FRMORM BBERRM TXERRM NYET ACKM NAKM STALLM Reserved CHHM XFRCM Reset value 0 0 0 0 0 0 0 0 0 0 0x52C OTG_FS_HCI NTMSK1 Reserved DTERRM...

Страница 1319: ...0 0 0 0 0 0 0 0 0 0 0 0x590 OTG_FS_HCT SIZ4 Reserved DPID PKTCNT XFRSIZ Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0x5B0 OTG_FS_HCT SIZ5 Reserved DPID PKTCNT XFRSIZ Rese...

Страница 1320: ...IS Reserved SNAK CNAK TXFNUM Stall Reserved EPT YP NAKSTS Reserved USBAEP Reserved MPSI Z Reset value 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0x918 TG_FS_DTXF STS0 Reserved INEPTFSAV Reset value 0 0 0 0 0 0 1 0...

Страница 1321: ...ODDFRM SD0PID SEVNFRM SNAK CNAK Reserved Stall SNPM EPTYP NAKSTS EONUM DPID USBAEP Reserved MPSIZ Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0xB60 OTG_FS_DOE PCTL3 EPENA EPDIS SODDFRM...

Страница 1322: ...0 0 0x950 OTG_FS_DIE PTSIZ2 Reserved MCN T PKTCNT XFRSIZ Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0x970 OTG_FS_DIE PTSIZ3 Reserved MCN T PKTCNT XFRSIZ Reset value 0 0...

Страница 1323: ...ion Memory map for the register boundary addresses 0xE00 OTG_FS_PCG CCTL Reserved PHYSUSP Reserved GATEHCLK STPPCLK Reset value Table 202 OTG_FS register map and reset values continued Offset Register...

Страница 1324: ...follow the initialization sequence irrespective of host or device mode operation All core global registers are initialized according to the core s configuration 1 Program the following fields in the...

Страница 1325: ...ister to select the size and the start address of the Non periodic transmit FIFO for non periodic transactions 14 Program the OTG_FS_HPTXFSIZ register to select the size and start address of the perio...

Страница 1326: ...ding short packets The application must program the PID field with the initial data PID to be used on the first OUT transaction or to be expected from the first IN transaction 6 Program the OTG_FS_HCC...

Страница 1327: ...s Writing the transmit FIFO The OTG_FS host automatically writes an entry OUT request to the periodic non periodic request queue along with the last DWORD write of a packet The application must ensure...

Страница 1328: ...ckets transfer size 1 024 bytes The non periodic transmit FIFO can hold two packets 128 bytes for FS The non periodic request queue depth 4 Normal bulk and control OUT SETUP operations The sequence of...

Страница 1329: ...UP and bulk control IN transactions a Bulk Control OUT SETUP Unmask NAK TXERR STALL XFRC ACK Host Application Device AHB USB OUT DATA0 MPS 1 MPS 1 MPS write_tx_fifo ch_1 init_reg ch_1 set_ch_en ch_2 i...

Страница 1330: ...ACK else Reset Error Count else if CHH Mask CHH if Transfer Done or Error_count 3 De allocate Channel else Re initialize Channel else if ACK Reset Error Count Mask ACK The application is expected to...

Страница 1331: ...lse if DTERR Reset Error Count The application is expected to write the requests as and when the Request queue space is available and until the XFRC interrupt is received Bulk and control IN transacti...

Страница 1332: ...ne the number of bytes received then read the receive FIFO accordingly Following this unmask the RXFLVL interrupt ACK Host Application Device AHB USB OUT DATA0 MPS 1 MPS 1 MPS write_tx_fifo ch_1 init_...

Страница 1333: ...e transfers Setup Data or Status stage OUT transactions are performed similarly to the bulk OUT transactions explained previously Data or Status stage IN transactions are performed similarly to the bu...

Страница 1334: ...ication Device AHB USB OUT DATA0 MPS 1 MPS 1 MPS write_tx_fifo ch_1 init_reg ch_1 set_ch_en ch_2 init_reg ch_2 write_tx_fifo ch_1 IN OUT DATA1 MPS Periodic Request Queue Assume that this queue can hol...

Страница 1335: ...H if Transfer Done or Error_count 3 De allocate Channel else Re initialize Channel in next b_interval 1 Frame else if ACK Reset Error Count Mask ACK The application uses the NPTXFE interrupt in OTG_FS...

Страница 1336: ...able Channel if STALL or BBERR Reset Error Count Transfer Done 1 else if FRMOR Reset Error Count else if TXERR Increment Error Count Unmask ACK Unmask CHH Disable Channel else if CHH Mask CHH if Trans...

Страница 1337: ...ts to send an IN token in the next odd frame e As soon as the IN packet is received and written to the receive FIFO the OTG_FS host generates an RXFLVL interrupt f In response to the RXFLVL interrupt...

Страница 1338: ...The periodic transmit FIFO can hold one packet 1 KB Periodic request queue depth 4 The sequence of operations is as follows a Initialize and enable channel 1 The application must set the ODDFRM bit i...

Страница 1339: ...ce AHB USB OUT DATA0 MPS 1 MPS 1 MPS write_tx_fifo ch_1 init_reg ch_1 set_ch_en ch_2 init_reg ch_2 write_tx_fifo ch_1 IN OUT DATA1 MPS Periodic Request Queue Assume that this queue can hold 4 entries...

Страница 1340: ...s IN Unmask TXERR XFRC FRMOR BBERR if XFRC or FRMOR if XFRC and OTG_FS_HCTSIZx PKTCNT 0 Reset Error Count De allocate Channel else Unmask CHH Disable Channel else if TXERR or BBERR Increment Error Cou...

Страница 1341: ...n must read and ignore the receive packet status when the receive packet status is not an IN data packet PKTSTS bit in OTG_FS_GRXSTSR 0b0010 h The core generates an XFRC interrupt as soon as the recei...

Страница 1342: ...bits INEP0 1 in OTG_FS_DAINTMSK control 0 IN endpoint OUTEP0 1 in OTG_FS_DAINTMSK control 0 OUT endpoint STUP 1 in DOEPMSK XFRC 1 in DOEPMSK XFRC 1 in DIEPMSK TOC 1 in DIEPMSK 3 Set up the Data FIFO R...

Страница 1343: ...endpoints that were active in the prior configuration or alternate setting are not valid in the new configuration or alternate setting These invalid endpoints must be deactivated 4 Unmask the interru...

Страница 1344: ...on can mask the RXFLVL interrupt in OTG_FS_GINTSTS by writing to RXFLVL 0 in OTG_FS_GINTMSK until it has read the packet from the receive FIFO 3 If the received packet s byte count is not 0 the byte c...

Страница 1345: ...O packet read SETUP transactions This section describes how the core handles SETUP packets and the application s sequence for handling SETUP transactions Application requirements 1 To receive a SETUP...

Страница 1346: ...e core internally sets the IN NAK and OUT NAK bits for the control IN OUT endpoints on which the SETUP packet was received 6 For every SETUP packet received on the USB 3 Words of data are written to t...

Страница 1347: ...FIFO Irrespective of the space availability in the receive FIFO non isochronous OUT tokens receive a NAK handshake response and the core ignores isochronous OUT data packets 2 The core writes the Glob...

Страница 1348: ...earlier it must be unmasked as follows GINAKEFFM 1 in GINTMSK Disabling an OUT endpoint The application must use this sequence to disable an OUT endpoint that it has enabled Application programming s...

Страница 1349: ...cket on the USB the core discards non isochronous OUT data packets that the host which cannot detect the ACK re sends The application does not detect multiple back to back data OUT packets on the same...

Страница 1350: ...acket count fields must always be set to the number of maximum packet size packets that can be received in a single frame and no more Isochronous OUT data transfers cannot span more than 1 frame 3 The...

Страница 1351: ...XDPID D1 in OTG_FS_DOEPTSIZx and the number of USB packets in which this payload was received 2 RXDPID D2 in OTG_FS_DOEPTSIZx and the number of USB packets in which this payload was received 3 The num...

Страница 1352: ...previous step must be performed before the SOF interrupt in OTG_FS_GINTSTS is detected to ensure that the current frame number is not changed 5 For isochronous OUT endpoints with incomplete transfers...

Страница 1353: ...he core internally sets the NAK bit for this endpoint to prevent it from receiving any more packets 5 The application processes the interrupt and reads the data from the RxFIFO 6 When the application...

Страница 1354: ...ndpoint NAK Internal data flow 1 When the application sets the IN NAK for a particular endpoint the core stops transmitting data on the endpoint irrespective of data availability in the endpoint s tra...

Страница 1355: ...rupt in OTG_FS_DIEPINTx indicates that the core has completely disabled the specified endpoint Along with the assertion of the interrupt the core also clears the following bits EPENA 0 in OTG_FS_DIEPC...

Страница 1356: ...the application must read the Transfer size register to determine how much data posted in the transmit FIFO have already been sent on the USB 4 Data fetched into transmit FIFO Application programmed i...

Страница 1357: ...ro length data packet the application must poll the OTG_FS_DTXFSTSx register where x is the FIFO number associated with that endpoint to determine whether there is enough space in the data FIFO The ap...

Страница 1358: ...FIFO mode for the frame is not present in the FIFO then the core generates an IN token received when TxFIFO empty interrupt for the endpoint A zero length data packet is transmitted on the USB for iso...

Страница 1359: ...ad is written to the FIFO In this case the application detects an IN token received when TxFIFO empty interrupt in OTG_FS_DIEPINTx The application can ignore this interrupt as it eventually results in...

Страница 1360: ...L bit must be set or cleared before the application sets up the Status stage transfer on the control endpoint Special case stalling the control OUT endpoint The core must stall IN OUT tokens if during...

Страница 1361: ...an IN token this information token received is synchronized to the AHB clock by the PFC the PFC runs on the AHB clock The PFC then reads the data from the SPRAM and writes them into the dual clock sou...

Страница 1362: ...turns off VBUS to conserve power SRP is a method by which the B device signals the A device to turn on VBUS power A device must perform both data line pulsing and VBUS pulsing but a host can detect e...

Страница 1363: ...device must detect SE0 for at least 2 ms to start SRP when VBUS power is off 4 To initiate SRP the device turns on its data line pull up resistor for 5 to 10 ms The OTG_FS controller detects data lin...

Страница 1364: ...the USB suspend bit in the Core interrupt register The OTG_FS controller informs the PHY to discharge VBUS 2 The PHY indicates the session s end to the device This is the initial condition for SRP Th...

Страница 1365: ...host role from the A device to the B device The application must set the HNP capable bit in the Core USB configuration register to enable the OTG_FS controller to perform HNP as an A device Figure 40...

Страница 1366: ...e mode operation 4 The B device detects the connection issues a USB reset and enumerates the OTG_FS controller for data traffic 5 The B device continues the host role initiating traffic and suspends t...

Страница 1367: ...pt register after 3 ms of bus idleness Following this the OTG_FS controller sets the USB suspend bit in the Core interrupt register The OTG_FS controller disconnects and the A device detects SE0 on th...

Страница 1368: ...witches back to the host role The OTG_FS controller deasserts the DP pull down and DM pull down in the PHY to indicate the assumption of the device role 6 The application must read the current mode bi...

Страница 1369: ...ly compliant with the On The Go Supplement to the USB 2 0 Specification It can also be configured as a host only or peripheral only controller fully compliant with the USB 2 0 Specification In host mo...

Страница 1370: ...HS FS low speed host A device An USB OTG FS dual role device It supports HS FS SOFs as well as low speed LS keep alive tokens with SOF pulse PAD output capability SOF pulse internal connection to tim...

Страница 1371: ...X FIFO and a nonperiodic TX FIFO for efficient usage of the USB data RAM It features dynamic trimming capability of SOF framing period in host mode 35 2 3 Peripheral mode features The OTG_HS interface...

Страница 1372: ...he ID line for A B Device identification DP DM integrated pull up and pull down resistors controlled by the OTG_HS core depending on the current role of the device As a peripheral it enables the DP pu...

Страница 1373: ...f the A side of the USB cable is connected with a grounded ID the OTG_HS issues an ID line status change interrupt CIDSCHG bit in the OTG_HS_GINTSTS register for host software initialization and autom...

Страница 1374: ...er SRPCAP bit in OTG_HS_GUSBCFG configures the OTG_HS to support the session request protocol SRP As a result it allows the remote A device to save power by switching VBUS off when the USB session is...

Страница 1375: ...e can also exit from the Suspended state by itself In this case the application sets the remote wakeup signaling bit in the device control register RWUSIG bit in OTG_HS_DCTL and clears it after 1 to 1...

Страница 1376: ...CTLx Endpoint enable disable Endpoint activation in current configuration Program the USB transfer type isochronous bulk interrupt Program the supported packet size Program the Tx FIFO number associat...

Страница 1377: ...the appropriate bit in this register to clear the corresponding bits in the DAINT and GINTSTS registers The peripheral core provides the following status checks and interrupt generation Transfer compl...

Страница 1378: ...V VBUS line The external charge pump can be driven by any GPIO output This is required for the OTG A host A device and host only configurations The VBUS input ensures that valid VBUS levels are suppli...

Страница 1379: ...a host port interrupt triggered by the device connected bit in the host port control and status PCDET bit in OTG_FS_HPRT Detection of peripheral disconnection by the host The peripheral disconnection...

Страница 1380: ...ore than 8 transfer requests are pending from the application the host controller driver HCD must re allocate channels when they become available that is after receiving the transfer completed and cha...

Страница 1381: ...eceived USB transaction error due to CRC failure timeout bit stuff error false EOP Babble error Frame overrun Data toggle error 35 6 4 Host scheduler The host core features a built in hardware schedul...

Страница 1382: ...d peripheral It also features an SOF pulse output connectivity These capabilities are particularly useful to implement adaptive audio clock generation techniques where the audio peripheral needs to sy...

Страница 1383: ...configuration register SOFOUTEN bit in OTG_HS_GCCFG The SOF pulse signal is also internally connected to the TIM2 input trigger so that the input capture feature the output compare feature and the ti...

Страница 1384: ...eiver is also disabled and only the part in charge of detecting the asynchronous resume or remote wakeup event is kept alive Gate HCLK GATEHCLK bit in OTG_HS_PCGCCTL When setting the Gate HCLK bit in...

Страница 1385: ...ck packets Typically two Largest Packet Size 4 1 spaces are recommended so that when the previous packet is being transferred to AHB the USB can receive the subsequent packet Along with each endpoints...

Страница 1386: ...ubsequent packet The minimum amount of RAM required for Host periodic Transmit FIFO is the largest maximum packet size for all supported periodic OUT channels If there is at least one High Bandwidth I...

Страница 1387: ...Core interrupt mask register OTG interrupt register Core interrupt register 1 Device IN OUT endpoint interrupt registers 0 to 5 Device all endpoints interrupt register 21 16 OUT endpoints 5 0 IN endp...

Страница 1388: ...ng Data FIFO access and host port control and status registers can be accessed in both host and peripheral modes When the OTG_HS controller is operating in one mode either peripheral or host the appli...

Страница 1389: ...this region 2 0000h 3 FFFFh Direct access to data FIFO RAM for debugging 128 Kbyte DFIFO debug read write to this region ai15615b Table 203 Core global control and status registers CSRs Acronym Addres...

Страница 1390: ...periodic transmit FIFO size register OTG_HS_HPTXFSIZ on page 1417 OTG_HS_DIEPTXFx 0x104 0x124 0x13C OTG_HS device IN endpoint transmit FIFO size register OTG_HS_DIEPTXFx x 1 7 where x is the FIFO_numb...

Страница 1391: ...30 Table 204 Host mode control and status registers CSRs continued Acronym Offset address Register name Table 205 Device mode control and status registers Acronym Offset address Register name OTG_HS_D...

Страница 1392: ...IZ0 on page 1453 OTG_HS_DIEPDMAx 0x914 OTG_HS device endpoint x DMA address register OTG_HS_DIEPDMAx OTG_HS_DOEPDMAx x 1 5 where x Endpoint_number on page 1457 OTG_HS_DTXFSTSx 0x918 OTG_HS device IN e...

Страница 1393: ...y unless otherwise specified OTG_HS control and status register OTG_HS_GOTGCTL Address offset 0x000 Reset value 0x0000 0800 The OTG control and status register controls the behavior and reflects the s...

Страница 1394: ...ime of a detected connection 0 Long debounce time used for physical connections 100 ms 2 5 s 1 Short debounce time used for soft connections 2 5 s Note Only accessible in host mode Bit 16 CIDSTS Conne...

Страница 1395: ...7 2 Reserved must be kept at reset value Bit 1 SRQ Session request The application sets this bit to initiate a session request on the USB The application can clear this bit by writing a 0 when the hos...

Страница 1396: ...essible in both peripheral and host modes Bits 16 10 Reserved must be kept at reset value Bit 9 HNSSCHG Host negotiation success status change The core sets this bit on the success or failure of a USB...

Страница 1397: ...TxFIFO is half empty 1 PTXFE in OTG_HS_GINTSTS interrupt indicates that the Periodic TxFIFO is completely empty Note Only accessible in host mode Bit 7 TXFELVL TxFIFO empty level In peripheral mode th...

Страница 1398: ...Forced peripheral mode After setting the force bit the application must wait at least 25 ms before the change takes effect Note Accessible in both peripheral and host modes Bit 29 FHMOD Forced host mo...

Страница 1399: ...carkit modes 0 PHY powers down the internal clock during suspend 1 PHY does not power down the internal clock Bit 18 ULPIAR ULPI Auto resume This bit sets the AutoResume bit in the interface control r...

Страница 1400: ...e Bit 6 PHSEL USB 2 0 high speed ULPI PHY or USB 1 1 full speed serial transceiver select 0 USB 2 0 high speed ULPI PHY 1 USB 1 1 full speed serial transceiver Bits 5 3 Reserved must be kept at reset...

Страница 1401: ...flushed using the TxFIFO Flush bit This field must not be changed until the core clears the TxFIFO Flush bit 00000 Nonperiodic TxFIFO flush in host mode Tx FIFO 0 flush in peripheral mode 00001 Period...

Страница 1402: ...ddle of a transaction The application must only write to this bit after checking that the core is neither reading from the RxFIFO nor writing to the RxFIFO The application must wait until the bit is c...

Страница 1403: ...lears the interrupts and all the CSR register bits except for the following bits RSTPDMODL bit in OTG_HS_PCGCCTL GAYEHCLK bit in OTG_HS_PCGCCTL PWRCLMP bit in OTG_HS_PCGCCTL STPPCLK bit in OTG_HS_PCGC...

Страница 1404: ...SOF OTGINT MMIS CMOD rc_w1 r r r rc_w1 r r rc_w1 r r r r rc_w1 r rc_w1 r Bit 31 WKUPINT Resume remote wakeup detected interrupt In peripheral mode this interrupt is asserted when a resume is detected...

Страница 1405: ...Sets a global nonperiodic IN NAK handshake Disables IN endpoints Flushes the FIFO Determines the token sequence from the IN token sequence learning queue Re enables the endpoints Clears the global non...

Страница 1406: ...te Only accessible in peripheral mode Bits 17 16 Reserved must be kept at reset value Bit 15 EOPF End of periodic frame interrupt Indicates that the period specified in the periodic frame interval fie...

Страница 1407: ...le in host mode Bit 4 RXFLVL RxFIFO nonempty Indicates that there is at least one packet pending to be read from the RxFIFO Note Accessible in both host and peripheral modes Bit 3 SOF Start of frame I...

Страница 1408: ...rw rw rw rw rw Bit 31 WUIM Resume remote wakeup detected interrupt mask 0 Masked interrupt 1 Unmasked interrupt Note Accessible in both host and peripheral modes Bit 30 SRQIM Session request new sessi...

Страница 1409: ...masked interrupt Note Only accessible in peripheral mode Bit 18 IEPINT IN endpoints interrupt mask 0 Masked interrupt 1 Unmasked interrupt Note Only accessible in peripheral mode Bit 17 EPMISM Endpoin...

Страница 1410: ...1 Unmasked interrupt Note Only accessible in peripheral mode Bit 5 NPTXFEM Nonperiodic TxFIFO empty mask 0 Masked interrupt 1 Unmasked interrupt Note Accessible in both peripheral and host modes Bit 4...

Страница 1411: ...ust only pop the Receive Status FIFO when the Receive FIFO nonempty bit of the Core interrupt register RXFLVL bit in OTG_HS_GINTSTS is asserted Host mode 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 1...

Страница 1412: ...f the received packet 0001 Global OUT NAK triggers an interrupt 0010 OUT data packet received 0011 OUT transfer completed triggers an interrupt 0100 SETUP transaction completed triggers an interrupt 0...

Страница 1413: ...12 11 10 9 8 7 6 5 4 3 2 1 0 NPTXFD NPTXFSA r rw r rw Bits 31 16 NPTXFD Nonperiodic TxFIFO depth This value is in terms of 32 bit words Minimum value is 16 Maximum value is 1024 Bits 15 0 NPTXFSA Non...

Страница 1414: ...of free space available in the nonperiodic transmit request queue This queue holds both IN and OUT requests in host mode Peripheral mode has only IN requests 00 Nonperiodic transmit request queue is...

Страница 1415: ...I2 C slave on the USB 1 1 full speed serial transceiver corresponding to the one used by the core for OTG signalling Bit 25 Reserved must be kept at reset value Bit 24 ACK I2 C ACK This bit indicates...

Страница 1416: ...onality VBUS connection can be remapped on another general purpose input pad and monitored by software This option is only suitable for host only or device only applications 0 VBUS sensing available b...

Страница 1417: ...cation programmable ID field 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PTXFD PTXSA r r w r r w r r w r r w r r w r r w r r w r r w r r w r r w r r w r r w r...

Страница 1418: ...emory start address for IN endpoint transmit FIFOx The address must be aligned with a 32 bit memory location 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reser...

Страница 1419: ...the number of PHY clocks that constitute the required frame interval The application can write a value to this register only after the Port enable bit of the host port control and status register PENA...

Страница 1420: ...frame 0 send in even micro frame 1 send in odd micro frame Bits 30 27 Channel endpoint number Bits 26 25 Type 00 IN OUT 01 Zero length packet 11 Disable channel command Bit 24 Terminate last entry for...

Страница 1421: ...ss offset 0x418 Reset value 0x0000 0000 The host all channel interrupt mask register works with the host all channel interrupt register to interrupt the application when an event occurs on a channel T...

Страница 1422: ...1 10 9 8 7 6 5 4 3 2 1 0 Reserved PSPD PTCTL PPWR PLSTS Reserved PRST PSUSP PRES POCCHNG POCA PENCHNG PENA PCDET PCSTS r r rw rw rw rw rw r r rw rs rw rc_ w1 r rc_ w1 rc_ w0 rc_ w1 r Bits 31 19 Reserv...

Страница 1423: ...set bit or Port resume bit in this register or the Resume remote wakeup detected interrupt bit or Disconnect detected interrupt bit in the Core interrupt register WKUINT or DISCINT in OTG_HS_GINTSTS r...

Страница 1424: ...it 0 PCSTS Port connect status 0 No device is attached to the port 1 A device is attached to the port 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 CHENA CHDIS...

Страница 1425: ...be issued for this endpoint per micro frame When the SPLITEN bit is set 1 in OTG_HS_HCSPLTx this field indicates the number of immediate retries to be performed for a periodic split transaction on tr...

Страница 1426: ...plete split The application sets this bit to request the OTG host to perform a complete split transaction Bits 15 14 XACTPOS Transaction position This field is used to determine whether to send all fi...

Страница 1427: ...8 7 6 5 4 3 2 1 0 Reserved DTERR FRMOR BBERR TXERR NYET ACK NAK STALL AHBERR CHH XFRC rc_ w1 rc_ w1 rc_ w1 rc_ w1 rc_ w1 rc_ w1 rc_ w1 rc_ w1 rc_ w1 rc_ w1 rc_ w1 Bits 31 11 Reserved must be kept at...

Страница 1428: ...w Bits 31 11 Reserved must be kept at reset value Bit 10 DTERRM Data toggle error mask 0 Masked interrupt 1 Unmasked interrupt Bit 9 FRMORM Frame overrun mask 0 Masked interrupt 1 Unmasked interrupt B...

Страница 1429: ...ield to 1 directs the host to do PING protocol Note Do not set this bit for IN transfers If this bit is set for IN transfers it disables the channel Bits 30 29 DPID Data PID The application programs t...

Страница 1430: ...h it must be stored This register is incremented on every AHB transaction 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved PERSCHIVL Reserved Reserved PFI...

Страница 1431: ...eld to select the handshake the core sends on receiving a nonzero length data packet during the OUT transaction of a control transfer s Status stage 1 Send a STALL handshake on a nonzero length status...

Страница 1432: ...this bit only after making sure that the Global OUT NAK effective bit in the Core interrupt register GONAKEFF bit in OTG_HS_GINTSTS is cleared Bit 8 CGINAK Clear global IN NAK A write to this field c...

Страница 1433: ...nd the device does not receive signals on the USB The core stays in the disconnected state until the application clears this bit 0 Normal operation When this bit is cleared after a soft disconnect the...

Страница 1434: ...ller goes into Suspended state and an interrupt is generated to the application with Early suspend bit of the Core interrupt register ESUSP bit in OTG_HS_GINTSTS If the early suspend is asserted due t...

Страница 1435: ...M Reserved EPDM XFRCM rw rw rw rw rw rw rw rw Bits 31 10 Reserved must be kept at reset value Bit 9 BIM BNA interrupt mask 0 Masked interrupt 1 Unmasked interrupt Bit 8 TXFURM FIFO underrun mask 0 Mas...

Страница 1436: ...w rw rw rw rw rw rw Bits 31 10 Reserved must be kept at reset value Bit 9 BOIM BNA interrupt mask 0 Masked interrupt 1 Unmasked interrupt Bit 8 OPEM OUT packet error mask 0 Masked interrupt 1 Unmasked...

Страница 1437: ...point interrupt mask register works with the device endpoint interrupt register to interrupt the application when an event occurs on a device endpoint However the device all endpoints interrupt OTG_HS...

Страница 1438: ...8 7 6 5 4 3 2 1 0 Reserved VBUSDT rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw Bits 31 16 Reserved must be kept at reset value Bits 15 0 VBUSDT Device VBUS discharge time Specifies the VBUS dischar...

Страница 1439: ...ceived on the USB before the core can start transmitting on the AHB The threshold length has to be at least eight DWORDS The recommended value for RXTHRLEN is to be the same as the programmed AHB burs...

Страница 1440: ...14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved INEPTXFEM rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw Bits 31 16 Reserved must be kept at reset value Bits 15 0 INEPTXFEM IN EP Tx FIFO empty interrupt...

Страница 1441: ...t reset value Bit 17 OEP1INTM OUT Endpoint 1 interrupt mask bit Bits 16 2 Reserved must be kept at reset value Bit 1 IEP1INTM IN Endpoint 1 interrupt mask bit Bit 0 Reserved must be kept at reset valu...

Страница 1442: ...t Bit 2 Reserved must be kept at reset value Bit 1 EPDM Endpoint disabled interrupt mask 0 Masked interrupt 1 Unmasked interrupt Bit 0 XFRCM Transfer completed interrupt mask 0 Masked interrupt 1 Unma...

Страница 1443: ...ket error mask 0 Masked interrupt 1 Unmasked interrupt Bits 7 3 Reserved must be kept at reset value Bit 2 AHBERRM AHB error mask 0 Masked interrupt 1 Unmasked interrupt Bit 1 EPDM Endpoint disabled i...

Страница 1444: ...EONUM field to even frame Bit 27 SNAK Set NAK A write to this bit sets the NAK bit for the endpoint Using this bit the application can control the transmission of NAK handshakes on an endpoint The cor...

Страница 1445: ...this endpoint The application must program the even odd frame number in which it intends to transmit receive isochronous data for this endpoint using the SEVNFRM and SODDFRM fields in this register 0...

Страница 1446: ...endpoint 0 Bits 29 28 Reserved must be kept at reset value Bit 27 SNAK Set NAK A write to this bit sets the NAK bit for the endpoint Using this bit the application can control the transmission of NAK...

Страница 1447: ...FIFO to accommodate the incoming packet Irrespective of this bit s setting the core always responds to SETUP data packets with an ACK handshake Bit 16 Reserved must be kept at reset value Bit 15 USBAE...

Страница 1448: ...ts the Even Odd frame EONUM field to even frame Bit 27 SNAK Set NAK A write to this bit sets the NAK bit for the endpoint Using this bit the application can control the transmission of NAK handshakes...

Страница 1449: ...number in which it intends to transmit receive isochronous data for this endpoint using the SEVNFRM and SODDFRM fields in this register 0 Even frame 1 Odd frame DPID Endpoint data PID Applies to inter...

Страница 1450: ...Bits 31 14 Reserved must be kept at reset value Bit 13 NAK NAK interrupt The core generates this interrupt when a NAK is transmitted or received by the device In case of isochronous IN endpoints the i...

Страница 1451: ...e kept at reset value Bit 4 ITTXFE IN token received when TxFIFO is empty Applies to nonperiodic IN endpoints only Indicates that an IN token was received when the associated TxFIFO periodic nonperiod...

Страница 1452: ...NYET NYET interrupt The core generates this interrupt when a NYET response is transmitted for a nonisochronous OUT endpoint Bits 13 7 Reserved must be kept at reset value Bit 6 B2BSTUP Back to back S...

Страница 1453: ...14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved PKTCNT Reserved XFRSIZ rw rw rw rw rw rw rw rw rw Bits 31 21 Reserved must be kept at reset value Bits 20 19 PKTCNT Packet count Indicates the total number...

Страница 1454: ...served PKTCNT Reserved XFRSIZ rw rw rw rw rw rw rw rw rw rw Bit 31 Reserved must be kept at reset value Bits 30 29 STUPCNT SETUP packet count This field specifies the number of back to back SETUP data...

Страница 1455: ...w rw rw rw Bit 31 Reserved must be kept at reset value Bits 30 29 MCNT Multi count For periodic IN endpoints this field indicates the number of packets that must be transmitted per frame on the USB Th...

Страница 1456: ...l registers EPENA bit in OTG_HS_DOEPCTLx the core modifies this register The application can only read this register once the core has cleared the Endpoint enable bit 31 30 29 28 27 26 25 24 23 22 21...

Страница 1457: ...r this endpoint This field is decremented every time a packet maximum size or short packet is written to the RxFIFO Bits 18 0 XFRSIZ Transfer size This field contains the transfer size in bytes for th...

Страница 1458: ...tion sets this bit to gate HCLK to modules other than the AHB Slave and Master and wakeup logic when the USB is suspended or the session is not valid The application clears this bit when the USB is re...

Страница 1459: ...IDSCHGM Reserved PTXFEM HCIM PRTIM Reserved FSUSPM IPXFRM IISOOXFRM IISOIXFRM OEPINT IEPINT EPMISM Reserved EOPFM ISOODRPM ENUMDNEM USBRST USBSUSPM ESUSPM Reserved GONAKEFFM GINAKEFFM NPTXFEM RXFLVLM...

Страница 1460: ...0 0 0 1 1 1 0 1 1 0 1 0 0 0 0 0 0 1 0 0 0 0 0 0 1 0 0 1 0 0 0x104 OTG_HS_DIE PTXF1 INEPTXFD INEPTXSA Reset value 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0x108 OTG_HS_DIE PTXF2...

Страница 1461: ...CHENA CHDIS ODDFRM DAD MC EPTYP LSDEV Reserved EPDIR EPNUM MPSIZ Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0x580 OTG_HS_HC CHAR4 CHENA CHDIS ODDFRM DAD MC EPTYP LSDEV...

Страница 1462: ...ALL AHBERR CHH XFRC Reset value 0 0 0 0 0 0 0 0 0 0 0 0x524 OTG_HS_HCS PL1 SPLITEN Reserved COMPLSPLT XACTPOS HUBADDR PRTADDR Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0x528 OTG_HS_HCI NT1 Reser...

Страница 1463: ...PRTADDR Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0x5C8 OTG_HS_HCI NT6 Reserved DTERR FRMOR BBERR TXERR NYET ACK NAK STALL AHBERR CHH XFRC Reset value 0 0 0 0 0 0 0 0 0 0 0 0x5E4 OTG_HS_HCS PLT7...

Страница 1464: ...R FRMOR BBERR TXERR NYET ACK NAK STALL AHBERR CHH XFRC Reset value 0 0 0 0 0 0 0 0 0 0 0 0x50C OTG_HS_HCI NTMSK0 Reserved DTERRM FRMORM BBERRM TXERRM NYET ACKM NAKM STALLM CHHM XFRCM Reset value 0 0 0...

Страница 1465: ...RRM TXERRM NYET ACKM NAKM STALLM AHBERR CHHM XFRCM Reset value 0 0 0 0 0 0 0 0 0 0 0 0x66C OTG_HS_HCI NTMSK11 Reserved DTERRM FRMORM BBERRM TXERRM NYET ACKM NAKM STALLM AHBERR CHHM XFRCM Reset value 0...

Страница 1466: ...value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0x514 OTG_HS_HC DMA0 DMAADDR Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0x524 OTG_HS_HC DMA1 DMAA...

Страница 1467: ...0 0 0 0 0 0 0 0 0 0 0 0 0x808 OTG_HS_DST S Reserved FNSOF Reserved EERR ENUMSPD SUSPSTS Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0x810 OTG_HS_DIE PMSK Reserved BIM TXFURM Reserved INEPNEM INEPN...

Страница 1468: ...RRM Reserved BIM TXFURM Reserved INEPNEM INEPNMM ITTXFEMSK TOM Reserved EPDM XFRCM Reset value 0 0 0 0 0 0 0 0 0 0 0 0x900 OTG_HS_DIE PCTL0 EPENA EPDIS SODDFRM SD0PID SEVNFRM SNAK CNAK TXFNUM STALL Re...

Страница 1469: ...set value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0x9A0 OTG_HS_DIE PCTL5 EPENA EPDIS SODDFRM SD0PID SEVNFRM SNAK CNAK TXFNUM STALL Reserved EPTYP NAKSTS EONUM DPID USBAEP Reserved MPSIZ...

Страница 1470: ...BNA TXFIFOUDRN TXFE INEPNE Reserved ITTXFE TOC Reserved EPDISD XFRC Reset value 0 0 0 0 0 1 0 0 0 0 0 0x928 OTG_HS_DIE PINT1 Reserved NAK BERR PKTDRPSTS Reserved BNA TXFIFOUDRN TXFE INEPNE Reserved I...

Страница 1471: ...B28 OTG_HS_DO EPINT1 Reserved NYET Reserved B2BSTUP Reserved OTEPDIS STUP Reserved EPDISD XFRC Reset value 0 0 0 0 0 0 0xB48 OTG_HS_DO EPINT2 Reserved NYET Reserved B2BSTUP Reserved OTEPDIS STUP Reser...

Страница 1472: ..._HS_DIE PDMAB2 DMABADDR Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0x970 OTG_HS_DIE PTSIZ3 Reserved MCN T PKTCNT XFRSIZ Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0...

Страница 1473: ...the core s configuration 0xB50 OTG_HS_DO EPTSIZ2 Reserved RXDPID STUPCNT PKTCNT XFRSIZ Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0xB54 OTG_HS_DO EPDMA2 DMAADDR Reset va...

Страница 1474: ...bit in OTG_HS_HPRT to 1 This drives VBUS on the USB 4 Wait for the PCDET interrupt in OTG_HS_HPRT0 This indicates that a device is connecting to the port 5 Program the PRST bit in OTG_HS_HPRT to 1 Thi...

Страница 1475: ...receiving this interrupt Wait for the ENUMDNE interrupt in OTG_HS_GINTSTS This interrupt indicates the end of reset on the USB On receiving this interrupt the application must read the OTG_HS_DSTS reg...

Страница 1476: ...eive any packet Halting a channel The application can disable any channel by programming the OTG_HS_HCCHARx register with the CHDIS and CHENA bits set to 1 This enables the OTG_HS host to flush the po...

Страница 1477: ...g request entry to the request queue The application must wait for the response to the ping token a NAK ACK or TXERR interrupt before continuing the transaction or sending another ping token The appli...

Страница 1478: ...all packet statuses other than IN data packet bx0010 1 MPS or LPS FIFO space available Wait for Write 1 packet data to Transmit FIFO More packets to send Yes No No Read GNPTXSTS HPTXFSIZ registers for...

Страница 1479: ...d control OUT SETUP operations The sequence of operations for channel 1 is as follows a Initialize channel 1 b Write the first packet for channel 1 c Along with the last DWORD write the core writes an...

Страница 1480: ...USB on the go high speed OTG_HS RM0090 1480 1731 DocID018909 Rev 11 Figure 416 Normal bulk control OUT SETUP and bulk control IN transactions DMA mode...

Страница 1481: ...transactions Slave mode The channel specific interrupt service routine for bulk and control OUT SETUP transactions in Slave mode is shown in the following code samples Interrupt service routine for b...

Страница 1482: ...CHH Mask CHH if Transfer Done or Error_count 3 De allocate Channel else Re initialize Channel else if ACK Reset Error Count Mask ACK The application is expected to write the data packets into the tran...

Страница 1483: ...or Count The application is expected to write the requests as and when the Request queue space is available and until the XFRC interrupt is received Bulk and control IN transactions A typical bulk or...

Страница 1484: ...USB on the go high speed OTG_HS RM0090 1484 1731 DocID018909 Rev 11 Figure 418 Bulk control IN transactions DMA mode...

Страница 1485: ...n HCCHAR2 to write an IN request to the nonperiodic request queue c The core attempts to send an IN token after completing the current OUT transaction d The core generates an RXFLVL interrupt as soon...

Страница 1486: ...milarly to the bulk OUT transactions explained previously Data or Status stage IN transactions are performed similarly to the bulk IN transactions explained previously For all three stages the applica...

Страница 1487: ...DocID018909 Rev 11 1487 1731 RM0090 USB on the go high speed OTG_HS 1529 Figure 420 Normal interrupt OUT IN transactions DMA mode...

Страница 1488: ...909 Rev 11 Figure 421 Normal interrupt OUT IN transactions Slave mode Interrupt service routine for interrupt OUT IN transactions a Interrupt OUT Unmask NAK TXERR STALL XFRC FRMOR if XFRC Reset Error...

Страница 1489: ...in next b_interval 1 Frame else if ACK Reset Error Count Mask ACK The application is expected to write the data packets into the transmit FIFO when the space is available in the transmit FIFO and the...

Страница 1490: ...ask ACK Unmask CHH Disable Channel if STALL or BBERR Reset Error Count Transfer Done 1 else if FRMOR Reset Error Count else if TXERR Increment Error Count Unmask ACK Unmask CHH Disable Channel else if...

Страница 1491: ...times before switching to another channel c The OTG_HS host writes an IN request to the periodic request queue for each OTG_HS_HCCHAR2 register write with the CHENA bit set d The OTG_HS host attempts...

Страница 1492: ...of operations is as follows a Initialize and enable channel 1 The application must set the ODDFRM bit in OTG_HS_HCCHAR1 b Write the first packet for channel 1 For a high bandwidth isochronous transfe...

Страница 1493: ...DocID018909 Rev 11 1493 1731 RM0090 USB on the go high speed OTG_HS 1529 Figure 422 Normal isochronous OUT IN transactions DMA mode...

Страница 1494: ...D018909 Rev 11 Figure 423 Normal isochronous OUT IN transactions Slave mode Interrupt service routine for isochronous OUT IN transactions Code sample Isochronous OUT Unmask FRMOR XFRC if XFRC De alloc...

Страница 1495: ...ous IN Unmask TXERR XFRC FRMOR BBERR if XFRC or FRMOR if XFRC and OTG_HS_HCTSIZx PKTCNT 0 Reset Error Count De allocate Channel else Unmask CHH Disable Channel else if TXERR or BBERR Increment Error C...

Страница 1496: ...es an RXFLVL interrupt for the transfer completion status entry in the receive FIFO This time the application must read and ignore the receive packet status when the receive packet status is not an IN...

Страница 1497: ...is interrupt the application must determine that this is not due to an overcurrent condition another cause of the Port Disabled interrupt by checking POCA in OTG_HS_HPRT then perform a soft reset The...

Страница 1498: ...oon as the channel receives the grant from the arbiter arbitration is performed in a round robin fashion c The OTG_HS host starts writing the received data to the system memory as soon as the last byt...

Страница 1499: ...packet is received and written to the receive FIFO the OTG_HS host generates a CHH interrupt e In response to the CHH interrupt reinitialize the channel for the next transfer Isochronous OUT transact...

Страница 1500: ...tions channel x is as follows a Initialize and enable channel x as explained in Section Channel initialization b The OTG_HS host writes the start split request to the nonperiodic request after getting...

Страница 1501: ...TG_HS host generates the CHH interrupt after transferring the received data to the system memory h In response to the CHH interrupt de allocate or reinitialize the channel for the next start split Iso...

Страница 1502: ...N endpoint OUTEP0 1 in OTG_HS_DAINTMSK control 0 OUT endpoint STUP 1 in DOEPMSK XFRC 1 in DOEPMSK XFRC 1 in DIEPMSK TOC 1 in DIEPMSK 3 Set up the Data FIFO RAM for each of the FIFOs Program the OTG_HS...

Страница 1503: ...zation on SetConfiguration SetInterface command This section describes what the application must do when it receives a SetConfiguration or SetInterface command in a SETUP packet 1 When a SetConfigurat...

Страница 1504: ...meet the following conditions to set up the device core to handle traffic NPTXFEM and RXFLVLM in GINTMSK must be cleared 35 13 7 Operational model SETUP and OUT data transfers This section describes...

Страница 1505: ...Don t Care 0b00 These data indicate that an OUT data transfer for the specified OUT endpoint has completed After this entry is popped from the receive FIFO the core asserts a Transfer Completed inter...

Страница 1506: ...n The core reserves this space in the receive data FIFO to write SETUP data only and never uses this space for data packets 3 The application must read the 2 DWORDs of the SETUP packet from the receiv...

Страница 1507: ...g a SETUP packet error a host does not send more than three back to back SETUP packets to the same endpoint However the USB 2 0 specification does not limit the number of back to back SETUP packets a...

Страница 1508: ...st set the Global OUT NAK bit by programming the following field SGONAK 1 in OTG_HS_DCTL 2 Wait for the assertion of the GONAKEFF interrupt in OTG_HS_GINTSTS When asserted this interrupt indicates tha...

Страница 1509: ...all data to be received as part of the OUT transfer 2 For OUT transfers the transfer size field in the endpoint s transfer size register must be a multiple of the maximum packet size of the endpoint...

Страница 1510: ...data from the receive FIFO and writes it to external memory one packet at a time per endpoint 5 At the end of every packet write on the AHB to external memory the transfer size for the endpoint is de...

Страница 1511: ...isochronous OUT endpoint must be enabled after the EOPF OTG_HS_GINTSTS and before the SOF OTG_HS_GINTSTS Internal data flow 1 The internal data flow for isochronous OUT endpoints is the same as that f...

Страница 1512: ...ived 2 RXDPID D2 in OTG_HS_DOEPTSIZx and the number of USB packets in which this payload was received 3 The number of USB packets in which this payload was received Application programmed initial pack...

Страница 1513: ...isochronous OUT endpoints with incomplete transfers the application must discard the data in the memory and disable the endpoint by setting the EPDIS bit in OTG_HS_DOEPCTLx 6 Wait for the EPDIS inter...

Страница 1514: ...this endpoint to prevent it from receiving any more packets 5 The application processes the interrupt and reads the data from the RxFIFO 6 When the application has read all the data equivalent to XFR...

Страница 1515: ...ead modify write on the OTG_HS_DIEPCTLx register to avoid modifying the contents of the register except for setting the Endpoint Enable bit The application can write multiple packets for the same endp...

Страница 1516: ...e 1 The application must stop writing data on the AHB for the IN endpoint to be disabled 2 The application must set the endpoint in NAK mode SNAK 1 in OTG_HS_DIEPCTLx 3 Wait for the INEPNE interrupt i...

Страница 1517: ...Transfer size register to determine how much data posted in the transmit FIFO have already been sent on the USB 4 Data fetched into transmit FIFO Application programmed initial transfer size core upd...

Страница 1518: ...rrupt for the endpoint is generated and the endpoint enable is cleared Application programming sequence 1 Program the OTG_HS_DIEPTSIZx register with the transfer size and corresponding packet count 2...

Страница 1519: ...fore the IN token is received Even when 1 DWORD of the data to be transmitted per frame is missing in the transmit FIFO when the IN token is received the core behaves as when the FIFO is empty When th...

Страница 1520: ...ble the endpoint so that the data can be transmitted on the next IN token attempt 5 Asserting the XFRC interrupt in OTG_HS_DIEPINTx with no ITTXFE interrupt in OTG_HS_DIEPINTx indicates the successful...

Страница 1521: ...ronous IN transfer interrupt in OTG_HS_GINTSTS indicates an incomplete isochronous IN transfer on at least one of the isochronous IN endpoints 3 The application must read the Endpoint Control register...

Страница 1522: ...of data specified in the SETUP packet Then when the application receives this interrupt it must set the STALL bit in the corresponding endpoint control register and clear this interrupt 35 13 8 Worst...

Страница 1523: ...a smaller value for TRDT in OTG_HS_GUSBCFG Figure 427 has the following signals tkn_rcvd Token received information from MAC to PFC dynced_tkn_rcvd Doubled sync tkn_rcvd from PCLK to HCLK domain spr_r...

Страница 1524: ...host can detect either data line pulsing or VBUS pulsing for SRP HNP is a method by which the B device negotiates and switches to host role In Negotiated mode after HNP the B device suspends the bus a...

Страница 1525: ...NTSTS 6 The application must service the Session request detected interrupt and turn on the port power bit by writing the port power bit in the host port control and status register The PHY indicates...

Страница 1526: ...perform data line pulsing followed by VBUS pulsing 5 The host detects SRP from either the data line or VBUS pulsing and turns on VBUS The PHY indicates VBUS power on to the device 6 The OTG_HS control...

Страница 1527: ...ipheral mode operation 4 The B device detects the connection issues a USB reset and enumerates the OTG_HS controller for data traffic 5 The B device continues the host role initiating traffic and susp...

Страница 1528: ...it in the host port control and status register The OTG_HS controller sets the Early suspend bit in the Core interrupt register after 3 ms of bus idleness Following this the OTG_HS controller sets the...

Страница 1529: ...ontroller continues the host role of initiating traffic and when done suspends the bus by writing the Port suspend bit in the host port control and status register 5 In Negotiated mode when the A devi...

Страница 1530: ...ank Independent configuration for each memory bank Programmable timings to support a wide range of devices in particular Programmable wait states up to 15 Programmable bus turnaround cycles up to 15 P...

Страница 1531: ...ave interface enables internal CPUs and other bus master peripherals to access the external static memories AHB transactions are translated into the external device protocol In particular if the selec...

Страница 1532: ...an the memory size In this case the FSMC splits the AHB transaction into smaller consecutive memory accesses in order to meet the external data width AHB transaction size is smaller than the memory si...

Страница 1533: ...s 2 and 3 used to address NAND Flash devices 1 device per bank Bank 4 used to address a PC Card device For each bank the type of memory to be used is user defined in the Configuration register Figure...

Страница 1534: ...te memory space 10 Bank 1 NOR PSRAM 3 11 Bank 1 NOR PSRAM 4 1 HADDR are internal AHB address lines that are translated to external memory Table 212 External memory address Memory width 1 1 In case of...

Страница 1535: ...RAM controller The FSMC generates the appropriate signal timings to drive the following types of memories Asynchronous SRAM and ROM 8 bit 16 bit 32 bit PSRAM Cellular RAM Asynchronous mode Burst mode...

Страница 1536: ...nous muxed I Os AHB clock cycle HCLK 1 15 Data setup Duration of the data setup phase Asynchronous AHB clock cycle HCLK 1 256 Bust turn Duration of the bus turnaround phase Asynchronousand synchronous...

Страница 1537: ...ut enable NWE O Write enable NL NADV O Latch enable this signal is called address valid NADV by some NOR Flash devices NWAIT I NOR Flash wait input signal to the FSMC Table 218 Nonmultiplexed I Os PSR...

Страница 1538: ...NWE O Write enable NL NADV O Address valid PSRAM input memory signal name NADV NWAIT I PSRAM wait input signal to the FSMC NBL 1 O Upper byte enable memory signal name NUB NBL 0 O Lowed byte enable m...

Страница 1539: ...I Os Asynchronous R 8 16 Y Asynchronous W 8 16 Y Use of byte lanes NBL 1 0 Asynchronous R 16 16 Y Asynchronous W 16 16 Y Asynchronous R 32 16 Y Split into 2 FSMC accesses Asynchronous W 32 16 Y Split...

Страница 1540: ...s for read and write operations For example read operation can be performed in mode A and write in mode B If the extended mode is disabled EXTMOD bit is reset in the FSMC_BCRx register the FSMC can op...

Страница 1541: ...umber Bit name Value to set 31 20 Reserved 0x000 19 CBURSTRW 0x0 no effect on asynchronous mode 18 16 CPSIZE 0x0 no effect on asynchronous mode 15 ASYNCWAIT Set to 1 if the memory supports this featur...

Страница 1542: ...Don t care 27 24 DATLAT Don t care 23 20 CLKDIV Don t care 19 16 BUSTURN Time between NEx high to NEx low BUSTURN HCLK 15 8 DATAST Duration of the second access phase DATAST 1 HCLK cycles for write ac...

Страница 1543: ...accesses 1 NBL 1 0 are driven low during read access Figure 437 ModeA write accesses A 25 0 NOE ADDSET DATAST Memory transaction NEx D 15 0 HCLK cycles HCLK cycles NWE NBL 1 0 data driven by memory ai...

Страница 1544: ...nchronous mode 12 WREN As needed 11 WAITCFG Don t care 10 WRAPMOD 0x0 9 WAITPOL Meaningful only if bit 15 is 1 8 BURSTEN 0x0 7 Reserved 0x1 6 FACCEN Don t care 5 4 MWID As needed 3 2 MTYP 0 1 As neede...

Страница 1545: ...TLAT Don t care 23 20 CLKDIV Don t care 19 16 BUSTURN Time between NEx high to NEx low BUSTURN HCLK 15 8 DATAST Duration of the second access phase DATAST 1 HCLK cycles for write accesses 7 4 ADDHLD D...

Страница 1546: ...ith mode1 are the toggling of NWE and the independent read and write timings when extended mode is set Mode B A 25 0 NOE ADDSET DATAST 1 Memory transaction NEx D 15 0 HCLK cycles HCLK cycles NWE NADV...

Страница 1547: ...needed 11 WAITCFG Don t care 10 WRAPMOD 0x0 9 WAITPOL Meaningful only if bit 15 is 1 8 BURSTEN 0x0 7 Reserved 0x1 6 FACCEN 0x1 5 4 MWID As needed 3 2 MTYP 0 1 0x2 NOR Flash memory 1 MUXEN 0x0 0 MBKEN...

Страница 1548: ...ue to set 31 30 Reserved 0x0 29 28 ACCMOD 0x1 27 24 DATLAT Don t care 23 20 CLKDIV Don t care 19 16 BUSTURN Time between NEx high to NEx low BUSTURN HCLK 15 8 DATAST Duration of the second access phas...

Страница 1549: ...on asynchronous mode 18 16 CPSIZE 0x0 no effect on asynchronous mode 15 ASYNCWAIT Set to 1 if the memory supports this feature Otherwise keep at 0 14 EXTMOD 0x1 13 WAITEN 0x0 no effect on asynchronou...

Страница 1550: ...0 Duration of the first access phase ADDSET HCLK cycles for read accesses Minimum value for ADDSET is 0 Table 231 FSMC_BWTRx bit fields Bit number Bit name Value to set 31 30 Reserved 0x0 29 28 ACCMO...

Страница 1551: ...Mode D read accesses Figure 444 Mode D write accesses A 25 0 NOE ADDSET DATAST Memory transaction NEx D 15 0 HCLK cycles HCLK cycles NWE NADV data driven by memory ai15566 High ADDHLD HCLK cycles A 2...

Страница 1552: ...ode 12 WREN As needed 11 WAITCFG Don t care 10 WRAPMOD 0x0 9 WAITPOL Meaningful only if bit 15 is 1 8 BURSTEN 0x0 7 Reserved 0x1 6 FACCEN Set according to memory support 5 4 MWID As needed 3 2 MTYP 0...

Страница 1553: ...x0 19 16 BUSTURN Time between NEx high to NEx low BUSTURN HCLK 15 8 DATAST Duration of the second access phase DATAST 1 HCLK cycles for write accesses 7 4 ADDHLD Duration of the middle phase of the wr...

Страница 1554: ...CPSIZE 0x0 no effect on asynchronous mode 15 ASYNCWAIT Set to 1 if the memory supports this feature Otherwise keep at 0 14 EXTMOD 0x0 13 WAITEN 0x0 no effect on asynchronous mode 12 WREN As needed 11...

Страница 1555: ...ive and so they are not prolonged The data setup phase DATAST in the FSMC_BTRx register must be programmed so that WAIT can be detected 4 HCLK cycles before the end of memory transaction The following...

Страница 1556: ...is low Figure 447 and Figure 448 show the number of HCLK clock cycles that are added to the memory access after WAIT is released by the asynchronous memory independently of the above cases Figure 447...

Страница 1557: ...memory controller FSMC 1588 Figure 448 Asynchronous wait during a write access 1 NWAIT polarity depends on WAITPOL bit setting in FSMC_BCRx register 7 EMORY TRANSACTION 7 4 X DATA DRIVEN BY 3 AI C AD...

Страница 1558: ...MC samples the data and waits long enough to evaluate if the data are valid Thus the FSMC detects when the memory exits latency and real data are taken Other memories do not assert NWAIT during latenc...

Страница 1559: ...send clock pulses to the memory keeping the chip select and output enable signals valid and does not consider the data valid There are two timing configurations for the NOR Flash NWAIT signal in burs...

Страница 1560: ...t on synchronous read 18 16 CPSIZE As needed 0x1 for CRAM 1 5 15 ASCYCWAIT 0x0 14 EXTMOD 0x0 13 WAITEN Set to 1 if the memory supports this feature otherwise keep at 0 12 WREN no effect on synchronous...

Страница 1561: ...s Bit No Bit name Value to set 31 30 Reserved 0x0 29 28 ACCMOD 0x0 27 24 DATLAT Data latency 23 20 CLKDIV 0x0 to get CLK HCLK not supported 0x1 to get CLK 2 HCLK 19 16 BUSTURN Time between NEx high to...

Страница 1562: ...NBL outputs are not shown they are held low while NEx is active DDR DATA ADDR EMORY TRANSACTION BURST OF HALF WORDS X 7 I 6 7 4 7 4 CLOCK CLOCK 4 4 INSERTED WAIT STATE AI F CYCLES DATA Table 239 FSMC...

Страница 1563: ...2 MTYP 0 1 0x1 1 MUXEN As needed 0 MBKEN 0x1 Table 240 FSMC_BTRx bit fields Bit No Bit name Value to set 31 30 Reserved 0x0 29 28 ACCMOD 0x0 27 24 DATLAT Data latency 23 20 CLKDIV 0x0 to get CLK HCLK...

Страница 1564: ...ables the synchronous burst protocol during write operations The enable bit for synchronous read accesses is the BURSTEN bit in the FSMC_BCRx register 0 Write operations are always performed in asynch...

Страница 1565: ...the bank by the FSMC an AHB error is reported 1 Write operations are enabled for the bank by the FSMC default after reset Bit 11 WAITCFG Wait timing configuration The NWAIT signal indicates whether t...

Страница 1566: ...MTYP 1 0 Memory type Defines the type of external memory attached to the corresponding memory bank 00 SRAM default after reset for Bank 2 4 01 PSRAM CRAM 10 NOR Flash OneNAND Flash default after reset...

Страница 1567: ...modes as shown in the timing diagrams These bits are taken into account only when the EXTMOD bit in the FSMC_BCRx register is 1 00 access mode A 01 access mode B 10 access mode C 11 access mode D Bits...

Страница 1568: ...static banks A synchronous write access in burst or single mode and a synchronous read from the same or a different bank An asynchronous and a synchronous write to any static or dynamic memory bank e...

Страница 1569: ...Figure 434 to Figure 446 Example Mode1 write access DATAST 1 Data phase duration DATAST 1 2 HCLK clock cycles Note In synchronous accesses this value is don t care Bits 7 4 ADDHLD 3 0 Address hold ph...

Страница 1570: ...phase duration The programmed bus turnaround delay is inserted between a an asynchronous write transfer and any other asynchronous synchronous read or write transfer to from a static bank for a read...

Страница 1571: ...ation 2 HCLK clock cycles 1111 1111 DATAST phase duration 255 HCLK clock cycles default value after reset Note In synchronous accesses this value is don t care Bits 7 4 ADDHLD 3 0 Address hold phase d...

Страница 1572: ...Memory wait Minimum duration HCLK clock cycles of the command assertion Read Write AHB clock cycle HCLK 2 256 Memory hold Number of clock cycles HCLK to hold the address and the data in case of a writ...

Страница 1573: ...l to the FSMC Table 244 16 bit PC Card FSMC signal name I O Function A 10 0 O Address bus NIORD O Output enable for I O space NIOWR O Write enable for I O space NREG O Register signal indicating if ac...

Страница 1574: ...to define number of HCLK cycles for the three phases of any PC Card CompactFlash or NAND Flash access plus one parameter that defines the timing for starting driving the databus in the case of a write...

Страница 1575: ...idth of the NAND Flash PTYP 1 PWAITEN 0 or 1 as needed see section Common memory space timing register 2 4 FSMC_PMEM2 4 on page 1582 for timing configuration 2 The CPU performs a byte write in the com...

Страница 1576: ...ifferent ways by simply performing the operation described in step 5 a new random address can be accessed by restarting the operation at step 3 a new command can be sent to the NAND Flash device by re...

Страница 1577: ...ed with bank 2 and bank 3 respectively As a consequence no hardware ECC computation is available for memories connected to bank 4 The error correction code ECC algorithm implemented in the FSMC can pe...

Страница 1578: ...sses the odd byte on D15 8 and nCE1 accesses the even byte on D7 0 if A0 0 or the odd byte on D7 0 if A0 1 The full word is accessed on D15 0 if both nCE2 and nCE1 are low The memory space is selected...

Страница 1579: ...ts must be programmed as follows Table 246 16 bit PC Card signals and access type nCE2 nCE1 nREG nOE nWE nIORD nIOWR A10 A9 A7 1 A0 Space Access Type Allowed not Allowed 1 0 1 0 1 X X X X X Common Mem...

Страница 1580: ...w rw rw rw rw rw rw Bits 31 20 Reserved must be kept at reset value Bits 19 17 ECCPS 2 0 ECC page size Defines the page size for the extended ECC 000 256 bytes 001 512 bytes 010 1024 bytes 011 2048 by...

Страница 1581: ...t This value is mandatory for PC Cards 10 reserved do not use 11 reserved do not use Bit 3 PTYP Memory type Defines the type of device attached to the corresponding memory bank 0 PC Card CompactFlash...

Страница 1582: ...pt high level detection request disabled 1 Interrupt high level detection request enabled Bit 3 IREN Interrupt rising edge detection enable bit 0 Interrupt rising edge detection request disabled 1 Int...

Страница 1583: ...data for write access after the command deassertion NWE NOE for PC Card NAND Flash read or write access to common memory space on socket x 0000 0000 Reserved 0000 0001 1 HCLK cycle 1111 1110 254 HCLK...

Страница 1584: ...0000 0001 1 HCLK cycle 1111 1110 254 HCLK cycles 1111 1111 Reserved Bits 15 8 ATTWAIT 7 0 Attribute memory x wait time Defines the minimum number of HCLK 1 clock cycles to assert the command NWE NOE...

Страница 1585: ...which the databus is kept in HiZ after the start of a PC Card write access to I O space on socket x Only valid for write transaction 0000 0000 0 HCLK cycle 1111 1111 255 HCLK cycles default value aft...

Страница 1586: ...is field provides the value computed by the ECC computation logic Table 247 hereafter describes the contents of these bit fields Table 247 ECC result relevant bits ECCPS 2 0 Page size in bytes ECC bit...

Страница 1587: ...CPSIZE 2 0 ASYNCWAIT EXTMOD WAITEN WREN WAITCFG WRAPMOD WAITPOL BURSTEN Reserved FACCEN MWID 1 0 MTYP 0 1 MUXEN MBKEN 0018 FSMC_BCR4 Reserved CBURSTRW CPSIZE 2 0 ASYNCWAIT EXTMOD WAITEN WREN WAITCFG W...

Страница 1588: ...d FEMPT IFEN ILEN IREN IFS ILS IRS 0xA000 0084 FSMC_SR3 Reserved FEMPT IFEN ILEN IREN IFS ILS IRS 0xA000 00A4 FSMC_SR4 Reserved FEMPT IFEN ILEN IREN IFS ILS IRS 0xA000 0068 FSMC_PMEM 2 MEMHIZ 7 0 MEMH...

Страница 1589: ...e FMC performs only one access at a time to an external device The main features of the FMC controller are the following Interface with static memory mapped devices including Static random access memo...

Страница 1590: ...y for PSRAM and SDRAM In this case the AHB burst is broken into two FIFO entries At startup the FMC pins must be configured by the user application The FMC I O pins which are not used by the applicati...

Страница 1591: ...transactions on the AHB are split into consecutive 16 or 8 bit accesses The FMC Chip Select FMC_NEx does not toggle between the consecutive accesses 06 9 1 1 3 DUG PHPRU FRQWUROOHU 1 1 VLJQDOV 6KDUHG...

Страница 1592: ...ta width This may lead to inconsistent transfers Therefore some simple transaction rules must be followed AHB transaction size and memory data size are equal There is no issue in this case AHB transac...

Страница 1593: ...s mapping From the FMC point of view the external memory is divided into 6 fixed size banks of 256 Mbyte each see Figure 455 Bank 1 used to address up to 4 NOR Flash memory or PSRAM devices This bank...

Страница 1594: ...ks as shown in Table 249 ANK X 2 032 32 3UPPORTED MEMORY TYPE ANK X DDRESS 0 ARD 3 6 3 2 X X X X X X X X X X X ANK X ANK X ANK X 3 2 ANK X 3 2 ANK X LASH MEMORY Table 249 NOR PSRAM bank selection HADD...

Страница 1595: ...n next 128 Kbytes in the common attribute memory space Table 250 NOR PSRAM External memory address Memory width 1 1 In case of a 16 bit external memory width the FMC will internally use HADDR 25 1 to...

Страница 1596: ...to increment the address of the data section to access consecutive memory locations 37 4 3 SDRAM address mapping The HADDR 28 bit internal AHB address line 28 is used to select one of the two memory...

Страница 1597: ...arge is not supported FMC_A 10 must be connected to the external memory address A 10 but it will be always driven low Table 255 SDRAM address mapping with 8 bit data bus width 1 2 Row size configurati...

Страница 1598: ...Res Bank 1 0 Row 12 0 Column 8 0 BM0 Res Bank 1 0 Row 12 0 Column 9 0 BM0 Re s Bank 1 0 Row 12 0 Column 10 0 BM0 1 BANK 1 0 are the Bank Address BA 1 0 When only 2 internal banks are used BA1 must alw...

Страница 1599: ...tput enable and write enable delays up to 15 Independent read and write timings and protocol to support the widest variety of memories and timings Programmable continuous clock FMC_CLK output The FMC...

Страница 1600: ...cated registers see Section 37 5 6 NOR PSRAM controller registers The programmable memory parameters include access times see Table 258 and support for wait management for PSRAM and NOR Flash accessed...

Страница 1601: ...led address valid NADV by some NOR Flash devices NWAIT I NOR Flash wait input signal to the FMC Table 260 16 bit multiplexed I O NOR Flash memory FMC signal name I O Function CLK O Clock for synchrono...

Страница 1602: ...nal to the FMC NBL 3 O Byte3 Upper byte enable memory signal name NUB NBL 2 O Byte2 Lowed byte enable memory signal name NLB NBL 1 O Byte1 Upper byte enable memory signal name NLB NBL 0 O Byte0 Lower...

Страница 1603: ...8 16 N Synchronous R 16 16 Y Synchronous R 32 16 Y PSRAM multiplexed I Os and non multiplexed I Os Asynchronous R 8 16 Y Asynchronous W 8 16 Y Use of byte lanes NBL 1 0 Asynchronous R 16 16 Y Asynchro...

Страница 1604: ...y the internal clock HCLK This clock is not issued to the memory The FMC always samples the data before de asserting the NOE signal This guarantees that the memory data hold timing constraint is met m...

Страница 1605: ...nsactions for the supported modes followed by the required configuration of FMC _BCRx and FMC_BTRx FMC_BWTRx registers Figure 456 Mode1 read access waveforms Figure 457 Mode1 write access waveforms 3...

Страница 1606: ...t to 1 if the memory supports this feature Otherwise keep at 0 14 EXTMOD 0x0 13 WAITEN 0x0 no effect in asynchronous mode 12 WREN As needed 11 WAITCFG Don t care 10 WRAPMOD 0x0 9 WAITPOL Meaningful on...

Страница 1607: ...access waveforms 1 NBL 3 0 are driven low during the read access 7 4 ADDHLD Don t care 3 0 ADDSET Duration of the first access phase ADDSET HCLK cycles Minimum value for ADDSET is 0 Table 265 FMC_BTRx...

Страница 1608: ...me Value to set 31 21 Reserved 0x000 20 CCLKEN As needed 19 CBURSTRW 0x0 no effect in asynchronous mode 18 16 CPSIZE 0x0 no effect in asynchronous mode 15 ASYNCWAIT Set to 1 if the memory supports thi...

Страница 1609: ...cesses 7 4 ADDHLD Don t care 3 0 ADDSET 3 0 Duration of the first access phase ADDSET HCLK cycles for read accesses Minimum value for ADDSET is 0 Table 268 FMC_BWTRx bit fields Bit number Bit name Val...

Страница 1610: ...h Figure 460 Mode2 and mode B read access waveforms 1 NBL 3 0 are driven low during the read access Figure 461 Mode2 write access waveforms 3 4 4 34 EMORY TRANSACTION X CYCLES CYCLES 7 6 DATA DRIVEN B...

Страница 1611: ...1 21 Reserved 0x000 20 CCLKEN As needed 19 CBURSTRW 0x0 no effect in asynchronous mode 18 16 CPSIZE 0x0 no effect in asynchronous mode 15 ASYNCWAIT Set to 1 if the memory supports this feature Otherwi...

Страница 1612: ...s second phase DATAST HCLK cycles for read accesses 7 4 ADDHLD Don t care 3 0 ADDSET 3 0 Duration of the access first phase ADDSET HCLK cycles for read accesses Minimum value for ADDSET is 0 Table 271...

Страница 1613: ...deC read access waveforms Figure 464 ModeC write access waveforms The differences compared with mode1 are the toggling of NOE and the independent read and write timings 3 4 4 34 EMORY TRANSACTION X CY...

Страница 1614: ...ded 11 WAITCFG Don t care 10 WRAPMOD 0x0 9 WAITPOL Meaningful only if bit 15 is 1 8 BURSTEN 0x0 7 Reserved 0x1 6 FACCEN 0x1 5 4 MWID As needed 3 2 MTYP 1 0 0x02 NOR Flash memory 1 MUXEN 0x0 0 MBKEN 0x...

Страница 1615: ...0 29 28 ACCMOD 0x2 27 24 DATLAT Don t care 23 20 CLKDIV Don t care 19 16 BUSTURN Time between NEx high to NEx low BUSTURN HCLK 15 8 DATAST Duration of the second access phase DATAST HCLK cycles for wr...

Страница 1616: ...e to set 31 21 Reserved 0x000 20 CCLKEN As needed 19 CBURSTRW 0x0 no effect in asynchronous mode 18 16 CPSIZE 0x0 no effect in asynchronous mode 15 ASYNCWAIT Set to 1 if the memory supports this featu...

Страница 1617: ...cles 3 0 ADDSET 3 0 Duration of the first access phase ADDSET HCLK cycles for read accesses Minimum value for ADDSET is 1 Table 277 FMC_BWTRx bit fields Bit No Bit name Value to set 31 30 Reserved 0x0...

Страница 1618: ...67 Muxed read access waveforms Figure 468 Muxed write access waveforms The difference with mode D is the drive of the lower address byte s on the data bus 3 4 4 34 EMORY TRANSACTION X CYCLES CYCLES 7...

Страница 1619: ...x0 13 WAITEN 0x0 no effect in asynchronous mode 12 WREN As needed 11 WAITCFG Don t care 10 WRAPMOD 0x0 9 WAITPOL Meaningful only if bit 15 is 1 8 BURSTEN 0x0 7 Reserved 0x1 6 FACCEN 0x1 5 4 MWID As ne...

Страница 1620: ...l aligned to NOE NWE which toggles 2 The memory asserts the WAIT signal aligned to NEx or NOE NWE not toggling if then otherwise where max_wait_assertion_time is the maximum time taken by the memory t...

Страница 1621: ...ata size 8 bits FMC_CLK HCLK 4 If CLKDIV 1 MWID 16 bits AHB data size 8 bits FMC_CLK HCLK 2 NOR Flash memories specify a minimum time from NADV assertion to CLK high To meet this constraint the FMC do...

Страница 1622: ...hip Select signal when the last data is strobed Such transfers are not the most efficient in terms of cycles compared to asynchronous read operations Nevertheless a random asynchronous access would fi...

Страница 1623: ...ms Figure 472 Synchronous multiplexed read mode waveforms NOR PSRAM CRAM 1 Byte lane outputs BL are not shown for NOR access they are held high and for PSRAM CRAM access DGGU GDWD GDWD DGGU 0HPRU WUDQ...

Страница 1624: ...nous read 11 WAITCFG to be set according to memory 10 WRAPMOD 0x0 9 WAITPOL to be set according to memory 8 BURSTEN 0x1 7 Reserved 0x1 6 FACCEN Set according to memory support NOR Flash memory 5 4 MWI...

Страница 1625: ...ts are not shown they are held low while NEx is active DDR DATA ADDR EMORY TRANSACTION BURST OF HALF WORDS X 7 I 6 7 4 7 4 CLOCK CLOCK 4 4 INSERTED WAIT STATE AI F CYCLES DATA Table 282 FMC_BCRx bit f...

Страница 1626: ...needed 3 2 MTYP 1 0 0x1 1 MUXEN As needed 0 MBKEN 0x1 Table 283 FMC_BTRx bit fields Bit No Bit name Value to set 31 30 Reserved 0x0 29 28 ACCMOD 0x0 27 24 DATLAT Data latency 23 20 CLKDIV 0x0 to get...

Страница 1627: ...LKEN bit of the FMC_BCR2 4 registers is don t care It is only enabled through the FMC_BCR1 register Bank 1 must be configured in synchronous mode to generate the FMC_CLK continuous clock Note If CCLKE...

Страница 1628: ...ble bit This bit indicates whether write operations are enabled disabled in the bank by the FMC 0 Write operations are disabled in the bank by the FMC an AHB error is reported 1 Write operations are e...

Страница 1629: ...ries 00 8 bits 01 16 bits default after reset 10 32 bits 11 reserved do not use Bits 3 2 MTYP 1 0 Memory type Defines the type of external memory attached to the corresponding memory bank 00 SRAM defa...

Страница 1630: ...cycles 2 to issue to the memory before reading writing the first data This timing parameter is not expressed in HCLK periods but in FMC_CLK periods For asynchronous accesses this value is don t care 0...

Страница 1631: ...static banks A synchronous write access in burst or single mode and a synchronous read from the same or a different bank An asynchronous and a synchronous write to any static or dynamic memory bank e...

Страница 1632: ...Example Mode1 write access DATAST 1 Data phase duration DATAST 1 2 HCLK clock cycles Note In synchronous accesses this value is don t care Bits 7 4 ADDHLD 3 0 Address hold phase duration These bits a...

Страница 1633: ...ration The programmed bus turnaround delay is inserted between a an asynchronous write transfer and any other asynchronous synchronous read or write transfer to from a static bank for a read operation...

Страница 1634: ...ycles 1111 1111 DATAST phase duration 255 HCLK clock cycles default value after reset Bits 7 4 ADDHLD 3 0 Address hold phase duration These bits are written by software to define the duration of the a...

Страница 1635: ...emory wait Minimum duration in HCLK clock cycles of the command assertion Read Write AHB clock cycle HCLK 2 255 Memory hold Number of clock cycles HCLK during which the address must be held as well as...

Страница 1636: ...FMC Table 287 16 bit PC Card FMC signal name I O Function A 10 0 O Address bus NIORD O Output enable for I O space NIOWR O Write enable for I O space NREG O Register signal indicating if access is in...

Страница 1637: ...define number of HCLK cycles for the three phases of any PC Card CompactFlash or NAND Flash access plus one parameter that defines the timing for starting driving the data bus when a write access is...

Страница 1638: ...ash memory PC Card address mapping for timing configuration 4 The CPU performs a byte write to the common memory space with data byte equal to one Flash command byte for example 0x00 for Samsung NAND...

Страница 1639: ...e NAND Flash device by restarting at step 2 37 6 5 NAND Flash prewait functionality Some NAND Flash devices require that after writing the last part of the address the controller waits for the R NB si...

Страница 1640: ...Flash data bus and read write signals NCE and NWE each time the NAND Flash memory bank is active The ECC operates as follows When accessing NAND Flash memory bank 2 or bank 3 the data present on the D...

Страница 1641: ...mory space combined with nCE2 nCE1 Note that nREG must also be asserted low when accessing I O space Three type of accesses are allowed for a 16 bit PC Card Accesses to Common Memory space for data st...

Страница 1642: ...lock cycles 37 6 8 NAND Flash PC Card controller registers PC Card NAND Flash control registers 2 4 FMC_PCR2 4 Address offset 0x40 0x20 x 1 x 2 4 Reset value 0x0000 0018 X 0 0 0 1 0 1 X X 0 Attribute...

Страница 1643: ...fault 1111 16 HCLK cycles Note SET is MEMSET or ATTSET according to the addressed space Bits 12 9 TCLR 3 0 CLE to RE delay Sets time from CLE low to RE low in number of AHB clock cycles HCLK Time is t...

Страница 1644: ...bank is disabled default after reset 1 Corresponding memory bank is enabled Bit 1 PWAITEN Wait feature enable bit Enables the Wait feature for the PC Card NAND Flash memory bank 0 disabled 1 enabled...

Страница 1645: ...curred 1 Interrupt high level occurred Bit 0 IRS Interrupt rising edge status The flag is set by hardware and reset by software 0 No interrupt rising edge occurred 1 Interrupt rising edge occurred Not...

Страница 1646: ...duced by deasserting NWAIT 1111 1111 Reserved Bits 7 0 MEMSET 7 0 Common memory x setup time Defines the number of HCLK 1 clock cycles to set up the address before the command assertion NWE NOE for PC...

Страница 1647: ...of NWAIT 1111 1110 255 HCLK cycles wait cycle introduced by the card deasserting NWAIT 1111 1111 Reserved Bits 7 0 ATTSET 7 0 Attribute memory x setup time Defines the number of HCLK 1 clock cycles to...

Страница 1648: ...to assert the command SMNWE SMNOE for PC Card read or write access to I O space on socket x The duration for command assertion is extended if the wait signal NWAIT is active low at the end of the pro...

Страница 1649: ...the ECCPS field in the FMC_PCRx registers the CPU must read the computed ECC value from the FMC_ECCx registers It then verifies if these computed parity data are the same as the parity value recorded...

Страница 1650: ...ncy of 1 2 3 Cacheable Read FIFO with depth of 6 lines x32 bit 6 x14 bit address tag 37 7 2 SDRAM External memory interface signals At startup the SDRAM I O pins used to interface the FMC SDRAM contro...

Страница 1651: ...Typical number is 8 7 Configure the MRD field according to your SDRAM device set the MODE bits to 100 and configure the Target Bank bits CTB1 and or CTB2 in the FMC_SDCMR register to issue a Load Mod...

Страница 1652: ...the WP bit in the FMC_SDCRx register Figure 476 Burst write SDRAM access waveforms The SDRAM controller always checks the next access If the next access is in the same row or in another active row the...

Страница 1653: ...e column address 2 bits to select the internal bank and the active row and 1 bit to select the SDRAM device When the end of the row is reached in advance during an AHB burst read the data read in adva...

Страница 1654: ...uring the CAS latency period and the RPIPE delay if configured This is done by incrementing the memory address The following condition must be met RBURST control bit should be set to 1 in the FMC_SDCR...

Страница 1655: ...k boundary management When a read or write access crosses a row boundary if the next read or write access is sequential and the current access was performed to a row boundary the SDRAM controller exec...

Страница 1656: ...ad access crossing row boundary Figure 480 Write access crossing row boundary 3 6 ATA 3 2 3 3 OL A OL A OL B 2OW N NA N A 3 420 3 LATENCY 7 0RECHARGE CTIVATE 2OW 2EAD OMMAND 2OW N 42 3 6 ATA 3 2 3 3 N...

Страница 1657: ...ange is violated and an AHB error is generated SDRAM controller refresh cycle The Auto refresh command is used to refresh the SDRAM device content The SDRAM controller periodically issues auto refresh...

Страница 1658: ...nt to the memory before activating the Self refresh mode and the BUSY status flag remains set In Self refresh mode all SDRAM device inputs become don t care except for SDCKE which remains low The SDRA...

Страница 1659: ...by setting the MODE bits to 110 and by configuring the Target Bank bits CTB1 and or CTB2 in the FMC_SDCMR register 02 2 3 3 4 4 4 4N 4 4 T2 3 MIN 0 54 2 2 3 0 OR 2 4 54 2 2 3 5 3 ATA I T20 0RECHARGE...

Страница 1660: ...evice cannot remain in Power down mode longer than the refresh period and cannot perform the Auto refresh cycles by itself Therefore the SDRAM controller carries out the refresh operation by executing...

Страница 1661: ...d only Bit 12 RBURST Burst read This bit enables burst read mode The SDRAM controller anticipates the next read commands during the CAS latency and stores data in the Read FIFO 0 single read requests...

Страница 1662: ...bits 11 reserved do not use Bits 3 2 NR 1 0 Number of row address bits These bits define the number of bits of a row address 00 11 bit 01 12 bits 10 13 bits 11 reserved do not use Bits 1 0 NC 1 0 Numb...

Страница 1663: ...devices are used the FMC_SDTR1 and FMC_SDTR2 must be programmed with the same TWR timing corresponding to the slowest SDRAM device Bits 15 12 TRC 3 0 Row cycle delay These bits define the delay betwe...

Страница 1664: ...to CTB1 and CTB2 command bits This register is the same for both SDRAM banks Bits 3 0 TMRD 3 0 Load Mode Register to Active These bits define the delay between a Load Mode Register command and an Act...

Страница 1665: ...he register is 0 no refresh is carried out This register must not be reprogrammed after the initialization procedure to avoid modifying the refresh rate Each time a refresh pulse is generated this 13...

Страница 1666: ...Interrupt is disabled 1 An Interrupt is generated if RE 1 Bits 13 1 COUNT 12 0 Refresh Timer Count This 13 bit field defines the refresh rate of the SDRAM device It is expressed in number of memory c...

Страница 1667: ...KEN 0x08 FMC_BCR2 Reserved CBURSTRW CPSIZE 2 0 ASYNCWAIT EXTMOD WAITEN WREN WAITCFG WRAPMOD WAITPOL BURSTEN Reserved FACCEN MWID 1 0 MTYP 1 0 MUXEN MBKEN 0x10 FMC_BCR3 Reserved CBURSTRW CPSIZE 2 0 ASY...

Страница 1668: ...HIZ 7 0 MEMHOLD 7 0 MEMWAIT 7 0 MEMSET 7 0 0x88 FMC_PMEM3 MEMHIZ 7 0 MEMHOLD 7 0 MEMWAIT 7 0 MEMSET 7 0 0xA8 FMC_PMEM4 MEMHIZ 7 0 MEMHOLD 7 0 MEMWAIT 7 0 MEMSET 7 0 0x6C FMC_PATT2 ATTHIZ 7 0 ATTHOLD 7...

Страница 1669: ...troller FMC 1669 0x154 FMC_SDRTR Reserved REIE COUNT 12 0 CRE 0x158 FMC_SDSR Reserved BUSY MODES2 1 0 MODES1 1 0 RE Table 292 FMC register map continued Offset Register 31 30 29 28 27 26 25 24 23 22 2...

Страница 1670: ...ation is complete the core and the system may be restored and program execution resumed The debug features are used by the debugger host when connecting to and debugging the STM32F4xx MCUs Two interfa...

Страница 1671: ...supported by the ARM Cortex M4 with FPU core refer to the Cortex M4 with FPU r0p1 Technical Reference Manual and to the CoreSight Design Kit r0p1 TRM see Section 38 2 Reference ARM documentation 38 2...

Страница 1672: ...ay it is possible to activate the SWDP using only the SWCLK and SWDIO pins This sequence is 1 Send more than 50 TCK cycles with TMS SWDIO 1 2 Send the 16 bit sequence on TMS SWDIO 0111100111100111 MSB...

Страница 1673: ...ecause the deactivation of the JTAGSW pins is done in two cycles to guarantee a clean level on the nTRST and TCK input signals of the core Cycle 1 the JTAGSW input signals to the core are tied to 1 or...

Страница 1674: ...ll up JTDI Internal pull up JTMS SWDIO Internal pull up TCK SWCLK Internal pull down Once a JTAG IO is released by the user software the GPIO controller takes control again The reset states of the GPI...

Страница 1675: ...debug pins remember that they will be first configured either in input pull up nTRST TMS TDI or pull down TCK or output tristate TDO for a certain duration after reset until the instant when the user...

Страница 1676: ...ug support DBG RM0090 1676 1731 DocID018909 Rev 11 Figure 485 JTAG TAP connections OUNDARY SCAN 4 0 4234 ORTEX 4 0 4 3 4 3 N4234 4 3 N4234 4 4 4 4 4 4 37 0 34 XXX 3ELECTED 2 IS BIT WIDE 2 IS BIT WIDE...

Страница 1677: ...reset Only the DEV_ID 11 0 should be used for identification by the debugger programmer tools DBGMCU_IDCODE Address 0xE004 2000 Only 32 bits access supported Read only 31 30 29 28 27 26 25 24 23 22 21...

Страница 1678: ...e ARM documentation 38 6 4 Cortex M4 with FPU JEDEC 106 ID code The ARM Cortex M4 with FPU integrates a JEDEC 106 ID code It is located in the 4KB ROM table mapped on the internal PPB bus at address 0...

Страница 1679: ...ite request Bits 2 1 A 3 2 2 bit address sub address AP registers Bit 0 RnW Read request 1 or write request 0 When transferring data OUT Bits 34 3 DATA 31 0 32 bit data which is read following a read...

Страница 1680: ...ency 38 8 2 SW protocol sequence Each sequence consist of three phases 1 Packet request 8 bits transmitted by the host 2 Acknowledge response 3 bits transmitted by the target 3 Data transfer phase 33...

Страница 1681: ...inactive until the target reads this ID code The SW DP state machine is in RESET STATE either after power on reset or after the DP has switched from JTAG to SWD or after the line is high for more tha...

Страница 1682: ...accepted even if the write buffer is full Because of the asynchronous clock domains SWCLK and HCLK two extra SWCLK cycles are needed after a write transaction after the parity bit to make the write ef...

Страница 1683: ...pported AHB AP transactions bypass the FPB The address of the 32 bits AHP AP resisters are 6 bits wide up to 64 words or 256 bytes and consists of c Bits 7 4 the bits 7 4 APBANKSEL of the DP SELECT re...

Страница 1684: ...d controls transfers through the AHB interface size hprot status on current transfer address increment type 0x04 AHB AP Transfer Address 0x0C AHB AP Data Read Write 0x10 AHB AP Banked Data 0 Directly...

Страница 1685: ...Monitor Control Register enable the bit0 C_DEBUGEN of the Debug Halting Control and Status Register Table 302 Core debug registers Register Description DHCSR The 32 bit Debug Halting Control and Stat...

Страница 1686: ...xecuted any instructions In addition it is possible to program any debug features under System Reset Note It is highly recommended for the debugger host to connect set a breakpoint in the reset vector...

Страница 1687: ...packets and the ITM emits them Time stamping Timestamps are emitted relative to packets The ITM contains a 21 bit counter to generate the timestamp The Cortex M4 with FPU clock or the bit clock rate o...

Страница 1688: ...ess Write 0xC5ACCE55 to unlock Write Access to the other ITM registers E0000E80 ITM trace control Bits 31 24 Always 0 Bits 23 Busy Bits 22 16 7 bits ATB ID which identifies the source of the trace dat...

Страница 1689: ...er source is selected using the Trigger Event Register 0xE0041008 An event could be a simple event address match from an address comparator or a logic equation between 2 events The trigger source is o...

Страница 1690: ...trace pins assignment 38 16 1 Debug support for low power modes To enter low power mode the instruction WFI or WFE must be executed The MCU implements several low power modes which can either deactiva...

Страница 1691: ...required for watchdog purposes For the bxCAN the user can choose to block the update of the receive register during a breakpoint For the I2 C the user can choose to block the SMBUS timeout during a br...

Страница 1692: ...from Standby 1 FCLK On HCLK On In this case the digital part is not unpowered and FCLK and HCLK are provided by the internal RC oscillator which remains active In addition the MCU generate a system r...

Страница 1693: ...2 receive registers are frozen Bit 24 Reserved must be kept at reset value Bit 23 DBG_I2C3_SMBUS_TIMEOUT SMBUS timeout mode stopped when Core is halted 0 Same behavior as in normal mode 1 The SMBUS ti...

Страница 1694: ...e core is halted 1 The clock of the involved Timer counter is stopped when the core is halted 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved DBG_TIM11 _STOP DBG_TIM10 _STOP DBG_TIM9_ STOP rw...

Страница 1695: ...m encapsulates the trace source ID that is then captured by a trace port analyzer TPA The core embeds a simple TPIU especially designed for low cost debug consisting of a special version of the CoreSi...

Страница 1696: ...ynchronous Asynchronous mode 1 extra pin is needed Synchronous mode from 2 to 5 extra pins are needed depending on the size of the data trace port register 1 2 or 4 TRACECK TRACED 0 if port size is co...

Страница 1697: ...use bytes consisting of 1 bit LSB to indicate it is a DATA byte 0 or an ID byte 1 7 bits MSB which can be data or change of source ID trace one byte of auxiliary bits where each bit corresponds to one...

Страница 1698: ...trigger can only be generated by the DWT Refer to the registers DWT Control Register bits SYNCTAP 11 10 and the DWT Current PC Sampler Cycle Count Register The TPUI Frame synchronization packet 0x7F_F...

Страница 1699: ...nder reset is different from the one after reset release This is because the RC calibration is the default one under system reset and is updated at each system reset release Consequently the trace por...

Страница 1700: ...gers are indicated Bits 7 4 always 0 Bits 3 2 always 0 Bit 1 EnFCont In Sync Trace mode Select_Pin_Protocol register bit1 0 00 this bit is forced to 1 the formatter is automatically enabled in continu...

Страница 1701: ...d DBG_IWDG_STOP DBG_WWDG_STOP Reserved DBG_RTC_STOP DBG_TIM14_STOP DBG_TIM13_STOP DBG_TIM12_STOP DBG_TIM7_STOP DBG_TIM6_STOP DBG_TIM5_STOP DBG_TIM4_STOP DBG_TIM3_STOP DBG_TIM2_STOP Reset value 0 0 0 0...

Страница 1702: ...amming the internal Flash memory to activate secure boot processes etc The 96 bit unique device identifier provides a reference number which is unique for any device and in any context These bits can...

Страница 1703: ...0 29 28 27 26 25 24 23 22 21 20 19 18 17 16 U_ID 95 80 r r r r r r r r r r r r r r r r 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 U_ID 79 64 r r r r r r r r r r r r r r r r Bits 31 0 U_ID 95 64 95 64 Uniqu...

Страница 1704: ...gister PWR_CSR RCC Updated Figure 20 Simplified diagram of the reset circuit and minimum reset pulse duration guaranteed by pulse generator restricted to internal reset sources GPIOs Updated Section 8...

Страница 1705: ...e and Downcounting mode in Section 17 3 2 Counter modes and Section 17 3 3 Repetition counter Updated bits that control the dead time generation in Section 17 3 11 Complementary outputs and dead time...

Страница 1706: ...onnection in Section 14 4 3 Removed note 1 related to OC1M bits in Section 18 4 13 TIMx capture compare register 1 TIMx_CCR1 Updated TIMx_CCER bit description for TIM2 to TIM5 in Section 18 4 9 TIMx c...

Страница 1707: ...n address register 1 I2C_OAR1 Updated definition of PE bit and note related to SWRST bit moved note related to STOP bit to the whole register in Section 27 6 1 I2C Control register 1 I2C_CR1 USART Sec...

Страница 1708: ...B OTG FS Updated remote wakeup signaling bit and the resume interrupt in Section Suspended state Added peripheral register access in Section 34 16 OTG_FS control and status registerss Updated INEPTXSA...

Страница 1709: ...and transactions Removed caution note in Section 36 6 1 External memory interface signalss Updated Table 244 16 bit PC Card Updated step 3 in Section 36 6 4 NAND Flash operations Updated Figure 453 Ac...

Страница 1710: ...bit access type from rw to w and bit description updated in Section 10 5 3 DMA low interrupt flag clear register DMA_LIFCR and Section 10 5 4 DMA high interrupt flag clear register DMA_HIFCR Updated...

Страница 1711: ...t in Section 5 5 1 PWR power control register PWR_CR for STM32F42xxx and STM32F43xxx SYSCFG Added ADCxDC2 bit in Section 8 2 3 SYSCFG peripheral mode configuration register SYSCFG_PMC for STM32F42xxx...

Страница 1712: ...ces between Mode D and mode 1 in Section Mode D asynchronous access with extended address Updated NWAIT signal in Figure 447 Asynchronous wait during a read access Figure 448 Asynchronous wait during...

Страница 1713: ...requency value in description of OSPEEDR bits Corrected typos IDRy 15 0 replaced with IDRy in GPIOx_IDR register ODRy 15 0 replaced with ODRy in GPIOx_ODR register and OTy 1 0 replaced with OTy in GPI...

Страница 1714: ...CompactFlash operations Updated WREN bit in Table 226 Table 227 Table 228 Table 231 Table 234 Table 237 Table 240 and Table 244 Updated Section 36 5 4 NOR Flash PSRAM controller asynchronous transacti...

Страница 1715: ...7 Selecting an alternate function on STM32F42xxx and STM32F43xxx DMA Updated Section 10 3 7 Pointer incrementation and Section 10 3 11 Single and burst transfers INTERRUPTS AND EVENTS Updated Table 62...

Страница 1716: ...NAND Flash PC Card controller waveforms for common memory access Updated Section SRAM NOR Flash chip select control registers 1 4 FMC_BCR1 4 Section SRAM NOR Flash chip select timing registers 1 4 FM...

Страница 1717: ...G_MEMRMP LTDC Changed resolution do XGA 1024x768 in Section 16 2 LTDC main features Section 16 4 1 LTDC Global configuration parameters and updated Section 16 7 3 LTDC Active Width Configuration Regis...

Страница 1718: ...ad mode waveforms NOR PSRAM CRAM Updated DATLAT bits definition in Section SRAM NOR Flash chip select timing registers 1 4 FMC_BTR1 4 Updated FMC_BWTRx register address offsets in Table 292 FMC regist...

Страница 1719: ...x IWDG timeout period at 32 kHz LSI CRYPTO and HASH Removed STM32F405 407xx and STM32F42xx from the whole sections Removed STM32F405 407xx and STM32F42xx from the whole section TIM10 11 13 14 Added TI...

Страница 1720: ...Refresh Timer register FMC_SDRTR and updated definition of COUNT bits Updated EXTMOD definition in Section SRAM NOR Flash chip select control registers 1 4 FMC_BCR1 4 Updated ADDSET definition in Sect...

Страница 1721: ...Table 29 Stop mode entry and exit STM32F42xxx and STM32F43xxx Updated Section Entering Standby mode Section Exiting Standby mode and Table 30 Standby mode entry and exit RCC Updated bits 24 to 31 acc...

Страница 1722: ...200 TRDT values FMC Updated FMC_NL in Figure 454 FMC block diagram Updated Memory wait and Memory data bus high z parameters in Table 284 Programmable NAND Flash PC Card access parameters Updated Sect...

Страница 1723: ...ontroller LTDC Corrected the bit field for WHSTPOS in the second bullet point in Section Window in Section 16 4 2 Layer programmable parameters Advanced control timers TIM1 TIM8 Added the note in Sect...

Страница 1724: ...SMC_PME2 4 register in Section 36 5 5 Synchronous transactions Updated ATTSET ATTHOLD ATTHIZ bit field descriptions for FSMC_PATT2 4 register in Section 36 5 5 Synchronous transactions Updated IRS and...

Страница 1725: ...or FMC_SR2 4 in Section 37 6 8 NAND Flash PC Card controller registers Updated the section SDRAM initialization with the last item in the numbered list in Section 37 7 5 SDRAM controller registers Ren...

Страница 1726: ...ng registers 1 4 FSMC_BWTR1 4 and Section SRAM NOR Flash chip select timing registers 1 4 FSMC_BTR1 4 Updated note related to IRS and IFS bits in Section FIFO status and interrupt register 2 4 FSMC_SR...

Страница 1727: ...41 CRYP_DIN 745 CRYP_DMACR 747 CRYP_DOUT 746 CRYP_IMSCR 747 CRYP_IV0LR 751 CRYP_IV0RR 751 CRYP_IV1LR 752 CRYP_IV1RR 752 CRYP_K0LR 749 CRYP_K0RR 749 CRYP_K1LR 750 CRYP_K1RR 750 CRYP_K2LR 750 CRYP_K2RR...

Страница 1728: ...AECR 1207 ETH_MMCRFCECR 1206 ETH_MMCRGUFCR 1207 ETH_MMCRIMR 1204 ETH_MMCRIR 1202 ETH_MMCTGFCR 1206 ETH_MMCTGFMSCCR 1206 ETH_MMCTGFSCCR 1205 ETH_MMCTIMR 1205 ETH_MMCTIR 1203 ETH_PTPPPSCR 1214 ETH_PTPSS...

Страница 1729: ...1404 OTG_FS_GNPTXFSIZ 1279 1413 OTG_FS_GNPTXSTS 1279 1413 OTG_FS_GOTGCTL 1262 1393 OTG_FS_GOTGINT 1264 1395 OTG_FS_GRSTCTL 1268 1401 OTG_FS_GRXFSIZ 1278 1412 OTG_FS_GRXSTSP 1277 1411 OTG_FS_GRXSTSR 12...

Страница 1730: ...SPI_I2SCFGR 915 SPI_I2SPR 916 SPI_RXCRCR 914 SPI_SR 912 SPI_TXCRCR 914 SYSCFG_EXTICR1 293 299 SYSCFG_EXTICR2 293 300 SYSCFG_EXTICR3 294 300 SYSCFG_EXTICR4 295 301 SYSCFG_MEMRMP 291 296 T TIM2_OR 637 T...

Страница 1731: ...urchasers are solely responsible for the choice selection and use of ST products and ST assumes no liability for application assistance or the design of Purchasers products No license express or impli...

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