RS_Telecom IP
RM0082
768/844
Doc ID 018672 Rev 1
Internally, the master mode can select between four clock sources, then divide it or use as it
is (for configuration please refer to
Table 704: TDM_conf register (Offset 0x04)
). The 16 bit
divider allows division from 2 to 131072.
●
CLKSM is the slave mode input clock signal on the PL_GPIO35 pin.
●
ClkR_osci1 is the master clock crystal frequency 24 MHz.
34.4.3
TDM synchro block
Eight synchronization signals SYNC0-SYNC7 are generated by the TDM synchro block.
The SYNC0 signal is bidirectional - generated in master mode and recovered in slave mode.
The reference clock for the TDM synchro block is the int_CLK clock delivered by the TDM
clock block.
●
In slave mode, SYNC0 signal is sampled at CLKSM rate.
●
In master mode, SYNC0 is generated at int_CLK rate.
●
All other SYNCx signals are generated at int_CLK rate.
Externally, the TDM synchro block is connected to SYNC0 to SYNC7 pins.
a) SYNC1 to SYNC3 (and SYNC0, if used master mode) are generated from an
internal counter and can take a predefined shape. They can all be delayed with
respect to each other by 8, 16 or 32 bits (counted on int_CLK clocks).
Either of the following shapes can be generated for any of them:
Figure 84.
SYNC0 (slave/master) and SYNC1 to SYNC3 possible shaping
b) SYNC4 to SYNC7 are user defined. They are programmable bit by bit through a
memory (the sync memory). SYNC memory is 512 words wide (32 bits). Each
word defines the SYNCx signals for one timeslot.
Word0 defines the four waveforms for the first height bits of the frame.
In each word,
●
Byte0 defines the waveform for SYNC4,
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Byte1 defines the waveform for SYNC5,
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Byte2 defines the waveform for SYNC6 and
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Byte3 defines the waveform for SYNC7.
In each byte, the MSB is played first.
RIGHT channel
LEFT channel
RIGHT channel
LEFT channel
Serial aligned
Wideband delayed
Wideband aligned
Narrowband delayed
Narrowband aligned
I2S
byte N/2
byte N/2-1
byte N-1
byte0