DocID025202 Rev 7
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RM0365
Analog-to-digital converters (ADC)
392
15.6.2 ADC
common
control
register (ADCx_CCR, x=12)
Address offset: 0x08 (this offset address is relative to the master ADC base a
0x300)
Reset value: 0x0000 0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Res.
Res.
Res.
Res.
Res.
Res.
Res.
VBAT
EN
TS
EN
VREF
EN
Res.
Res.
Res.
Res.
CKMODE[1:0]
rw
rw
rw
rw
rw
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
MDMA[1:0]
DMA
CFG
Res.
DELAY[3:0]
Res.
Res.
Res.
DUAL[4:0]
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
Bits 31:25 Reserved, must be kept at reset value.
Bit 24
VBATEN
: V
BAT
enable
This bit is set and cleared by software to enable/disable the V
BAT
channel.
0: V
BAT
channel disabled
1: V
BAT
channel enabled
Note: Software is allowed to write this bit only when the ADCs are disabled (ADCAL=0,
JADSTART=0, ADSTART=0, ADSTP=0, ADDIS=0 and ADEN=0).
Bit 23
TSEN
: Temperature sensor enable
This bit is set and cleared by software to enable/disable the temperature sensor channel.
0: Temperature sensor channel disabled
1: Temperature sensor channel enabled
Note: Software is allowed to write this bit only when the ADCs are disabled (ADCAL=0,
JADSTART=0, ADSTART=0, ADSTP=0, ADDIS=0 and ADEN=0).
Bit 22
VREFEN
: V
REFINT
enable
This bit is set and cleared by software to enable/disable the V
REFINT
channel.
0: V
REFINT
channel disabled
1: V
REFINT
channel enabled
Note: Software is allowed to write this bit only when the ADCs are disabled (ADCAL=0,
JADSTART=0, ADSTART=0, ADSTP=0, ADDIS=0 and ADEN=0).
Bits 21:18 Reserved, must be kept at reset value.