MACH16
S
LIM
L
ITE
3Gbps
SATA
S
TANDARD
S
OLID
-S
TATE
D
RIVE
P
ART
N
UMBER
:
M16SD2S(3)-
XXX
U(T)(X)-XXX
D
OCUMENT
N
UMBER
:
61000-07132-311
R
EVISION
N
UMBER
:
3.11
R
EVISION
D
ATE
:
01/15/2013
39
I
NTERFACE
S
PECIFICATIONS
O
VERVIEW
The SSD is comprised of the following functional blocks: the interface connector, an ASIC with an
integrated processor, NAND flash memory and DRAM cache. Read/Write data transfer requests are
initiated by the host via the SATA bus interface. Once received, the requests are processed by the ASIC
controller under the direction of the microprocessor. The controller interfaces with the NAND flash devices
and sequences the data flow between the DRAM cache and NAND flash.
M
ICROCONTROLLER
The microcontroller is responsible for initiating and controlling all activity within the controller, including
bad block mapping and executing the wear-leveling algorithms. The controller decodes an incoming host
command, and will configure the appropriate interrupts and status for the local microprocessor to handle
various ATA commands. For read and write transfer commands, the hardware can handle the initial
handshake with the host automatically. If firmware enables full auto mode, read and write transfers can
be fully handled by hardware with minimum firmware support.
R
EAD AND
W
RITE
C
OMMANDS
Commands that do not require data to be read from or written to the flash memory controller are typically
handled by the controller. Some commands may require the controller to use external circuitry that does
not involve the flash memory controller.
U
SER
D
ATA
C
ACHE
The SSD is configured with 256MB of DRAM, of which a portion is reserved for the user data cache. The
write data can be flushed from the cache to the flash with the FLUSH CACHE (E7h) or FLUSH CACHE
EXT (EAh) commands.
W
RITE
O
PERATIONS
When a write operation is requested and data is received, the controller uses integrated DMA controllers
to transfer the data from host memory to the flash memory controller. The flash memory controller
transfers the data from the controller to available locations in the local flash memory of the SSD. The
controller notifies the host after the write operation is completed.
R
EAD
R
EQUESTS
If a read request is received via the SATA interface, the controller retrieves the data from the local flash
memory via the flash memory controller. The controller notifies the host with status when the data is ready
for transmission. The drive supports UDMA and PIO modes to maintain backward compatibility.
A
CTIVITY
LED
The SSD is configured to drive Pin P11, DAS (Drive Activity Signal) of the Serial ATA cable during all
command activity and during periods when the drive indicates a busy state. See
Interface Connector
.
