4
Figure 2-2 Receiver block diagram
Antenna LPF
Antenna
JT01
Antenna switch
BPF
BPF
First mixer
Crystal filter
First IF AMP
From VCO circuit
first local signal
To second IF IC pin 20
CT62, CT52, RT58,
LT05, CT61, LT07,
QT04
UM9401
LR01
LR02
QR30
2SC2714(Y)
FR30, FR31
21.40 MHz
QR04
2SK508(K53)
LR04
LR05
LR06
RF AMP
QR02
2SK508(K53)
QR01
DAP202U
Protection
Circuit
Protection
Circuit
QT05
DA204U
CT64, CT63, LT06,
CT65, LT08, CT66
CT67
2.1.6 Unlock Detector Circuit
The PLL circuit is locked or unlocked (operational / not opera-
tional) depending on the output of pin 7 of PLL IC QP02.
When there is no phase difference between the reference and
programmable frequencies in the phase comparator of PLL
IC QP02, the PLL circuit is locked and a 5.1 V level is output
from the phase comparator, pin 7 of QP02. It is applied to the
unlock detector circuit, QP03 and QP07, turning QP03 off. 0V
level is applied to pin 13 of microprocessor QL01 when QP03
is off. With the signal, the PLL circuit is determined that it locked,
to supply the N number to the PLL IC QP02.
When there is a phase difference between the reference and
programmable frequencies in QP02, the PLL circuit is unlocked
and a 2.5 V level is output from pin 7 of PLL IC QP02. It is
applied to the unlock detector circuit, QP03 and QP07, turn-
ing QP03 on. A 5.1 V level is applied to pin 13 of microproces-
sor QL01 when QP03 is on. It determined the PLL circuit is
unlocked when pin 13 of microprocessor QL01 is 5.1 V level,
to keep the N number from being supplied to the PLL IC QP02.
2.2 Receiver
Refer to Figure 2-2.
The receiver is a double-conversion super-heterodyne with a first intermediate frequency (lF) of 21.4 MHz and a second IF of 455
kHz.
The receiver circuit consists of RF amplifier QR02, first mixer QR04, first IF amplifier QR30, second lF AMP circuit QR60, audio
circuits Q101, Q107 to operate in the frequency range of 156.050 to 163.275 MHz.
2.2.1 RF
Amplifier
Circuit
The incoming signal through the antenna socket (JT01) passes
through the low pass filter comprised of CT64, CT63, LT06,
CT62, CT52, RT58, LT05, CT61, LT07, CT65, LT08, CT66,
and CT67. It then passes through antenna switch QT04 and
the over input protection circuit QT05 and is applied to the
band-pass filter. The receiving frequency is passed through
the band-pass filter comprised of LR01 and LR02 and is ap-
plied to RF amplifier QR02. The incoming receive frequency is
amplified by QR02 and applied to another narrow band-pass
filter comprised of LR04, LR05, and LR06 to eliminate un-
wanted signals. The receiving frequency is then applied to the
gate of first mixer QR04. The front-end test point (TP04) may
be used to balance the band-pass filters, or used to check if
the RF Amplifier and associated circuitry are operational.
2.2.2 First
Mixer
Circuit
The first local signal is applied to the source of first mixer QR04,
The receive frequency and the first local signal are mixed in
QR04 and produce four frequencies (the sum, the difference,
receive, and LO). The first LO is comprised of the RX frequency
minus 21.4 MHz. These signals are applied to the crystal filter
comprised of FR30 and FR31. A 21.4 MHz signal is filtered
from the adjacent signals. The first IF signal of 21.4 MHz is
then applied to first IF amplifier QR30.
2.2.3 First
lF
Amplifier
The 21.4 MHz first IF signal is amplified by QR30 and then
applied to pin 20 of second IF IC QR60.
The local test point (TP05) may be used to balance the LO
band-pass filters, or used to check if the VCO (first LO) and
associated circuitry are operational.
