Obsolete Product(s) - Obsolete Product(s)
STMicroelectronics Confidential
19/62
AN1290 Horizontal
Section
pitch, the wider the stripes (however, if the dot array is not uniform, the basically vertical stripes will
be strongly distorted).
Please notice that if the succession of dots is shifted horizontally by half a pixel, the dark and bright
stripes will be exchanged. This provides a way to compensate the H Moire: by artificially introducing
an horizontal jitter with an amplitude of half a pixel, any point on the screen will be successively on
a dark then bright stripe. As a result the eye will see medium brightness everywhere.
Since Moire can also appear with other less simple combinations of dots and pixels, the setting of
the Moire cancellation must be left to the end user for optimum results.
A self-contained H-Moire cancellation system is available on the TDA9112: an internal logic circuit
provides a series of pulses related to H frequency with an adjustable amplitude through I²C
(Register 02). After a convenient attenuation, this pulsed voltage will modulate the voltage on PLL2
capacitor, introducing the required artificial H jitter. The phase of this jitter is reversed for every other
frame, in order to make it less noticeable.
This Moire cancellation system can be used for any type of monitor (be it common or separate EHV
and H scanning). Two modes can be selected through I²C programming (Sad02h/d7). In the event
of a “common” structure, better results will be obtained when set to 0, while 1 is mandatory with a
“separate” structure. If Moire is not needed, the level must be set to 0 through I²C programming.
On the low-cost TDA9115 version, the Moire compensation is available on pin 11 rather than being
applied internally. First, the pulse amplitude of pin 11 must be divided in a ratio of 1000 to 2000 with
a resistor bridge referenced to HGND. Then connect the low-side end of PLL2 capacitor (formerly
grounded) to the medium point of resistor bridge. This way, the compensation pulses will be applied
to pin 5 through the capacitor.
The TDA9116 provides either internal or external compensation which is selected by I²C
programming (Sad16h/d3:2). When internal compensation is selected, pin 11 becomes a 7-bit DAC
with a span between 0 and 5 V.
4.2
Application Hints
4.2.1
Minimizing Jitter
The TDA9112 provides low intrinsic horizontal jitter, but some care must be taken not to spoil its
naturally good performances. Since all horizontal timings are based on the comparison of the
oscillator sawtooth with various DC levels, all these voltages should be kept perfectly clean. Let us
make a “rule-of-thumb” calculation: if the oscillator sawtooth amplitude: 4.8V, corresponds to 7/8 of
the period, then a 1mV parasitic voltage on either the sawtooth or one of the DC levels will induce:
31778 x (7/8)/4800 = 5.8 ns of jitter in VGA, which is an unacceptable value.
Here are some basic precautions to obtain the best jitter value:
●
First, care should be taken not to corrupt the incoming sync pulse. Typically, it will have some
20ns transition time and an 5V amplitude. In these conditions, adding a 0.25 V amplitude
parasitic voltage (ground ripple for instance) will cause 1ns of jitter on the incoming sync.
Similar considerations apply to Hfly pulse, which is not very fast.
More precisely, we can consider that the components of the PLL1 filter have been optimized for
jitter. If jitter is found to decrease when using other values than the ones indicated for theses
components, usually the reason is that the input HSync is already jittered; suppressing this
jitter on the HSync input will lead to a jitter performance unattainable before.
●
A separate ground connection, tied to pin 7, should be devoted to all horizontal-related
components, i.e. those connected to pins 4, 5, 6, 8, 9, 10, 12 and 13. This connection must be
tied to pins 21 and 27, but it should not carry any other current, especially those not
