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Figure 10. 

Clock generation and clock tree

÷ DIVM1                

÷ DIVM2                

÷ DIVM3                

PLLSRC

1 to 16 

MHz

0

1
2

hsi_ck
csi_ck
hse_ck

ref1_ck

ref3_ck

ref2_ck

OSC32_IN

OSC32_OUT

OSC_IN

OSC_OUT

LSE

HSE

VSW (Backup)

HSI

CSI

HSI48

lse_ck

hse_ck

hsi_ck

csi_ck

hsi48_ck

CSS

hsi_ck

csi_ck

hse_ck

To 

peripherals

To CPU, 

busses and

peripherals

0

1
2
3

pll1_q_ck

pll1_r_ck

pll2_p_ck

pll2_q_ck
pll2_r_ck

pll3_p_ck

pll3_q_ck
pll3_r_ck

pll1_p_ck

1 to 16 

MHz

1 to 16 

MHz

SW

pll1_p_ck

sys_ck

0

1
2
3
4
5

÷ 1 to15                

MCO2PRE

MCO2SEL

0

1
2
3
4

÷ 1 to15                

MCO1PRE

MCO1SEL

pll[3:1]_q_ck

pll[3:2]_p_ck

pll[3:2]_r_ck

sys_ck

hse_ck

hsi_ker_ck

csi_ker_ck

per_ck

lsi_ck

lse_ck

hsi48_ck

MCO2

MCO1

I2S_CKIN

USB_PHY1

ETH_MII_TX_CLK

ulpi1_phy_ck

RCC

lse_ck

lsi_ck

hse_1M_ck

1
2
3

÷ 2 to 63                

RTCPRE

RTCSRC

hsi_ker_ck

csi_ker_ck

hse_ck

CKPERSRC

per_ck

0

1
2

To 

RTC/AWU

RTCEN

To 

IWDG1

tempo

÷

1

,2,4,8                

HSION

CSION

HSI48ON

HSIDIV

HSEON

SCGU

  

(System Clock

 

Generation

)

rcc_rtc_ck

PKEU 

(Peripheral

 Clock Enabling

)

CSS

LSEON

pll1_r_ck

traceclkin

To TPIU

CRS

Clock 

recovery 

system

VCO

PLL1

DIVN1

FRACN1

VCO

PLL2

DIVN2

FRACN2

LSI

lsi_ck

tempo

LSION or IWDG1 activated

VDD Domain

SCEU 

(System Clock 

Enabling

)

D

D

The selected input can be changed on-the-fly without spurs on the output signal

sys_ck

pll2_p_ck

hse_ck

pll1_p_ck

csi_ck

lsi_ck

hsi_ck

lse_ck

hse_ck

pll1_q_ck

hsi48_ck

hsi_ck

csi_ck

hse_ck

0

1
2
3

x

 Represents the selected mux input after a system reset

0

0

VDD Domain

csi_ker_ck

tempo

tempo

hsi_ker_ck

tempo

HSIKERON

CSIKERON

D

ETH_MII_RX_CLK
ETH_RMII_REF_CLK

D

PKSU

 

(Peripheral

 Kernel

 clock Selection

)

DIVP1

DIVQ1

DIVR1

DIVP2

DIVQ2

DIVR2

VCO

PLL3

FRACN3

DIVP3

DIVQ3

DIVR3

DIVN3

Table 3. 

Clock connections

Pin

External component

Comment

OSC32_IN

External clock input

LSE oscillator

LSE bypass input f≤ 1 MHz.

AN5419

Introduction

AN5419

 - 

Rev 2

page 19/50

Содержание STM32H723

Страница 1: ...and STM32H730 microcontrollers Reference documents STM32H72x and STM32H73x datasheets STM32H723 733 STM32H725 735 and STM32H730 advanced Arm based 32 bit MCUs RM0468 STM32H723 733 STM32H725 735 and ST...

Страница 2: ...ent applies to STM32H723 33 STM32H725 35 and STM32H730Arm based microcontroller lines Note Arm is a registered trademark of Arm Limited or its subsidiaries in the US and or elsewhere AN5419 General in...

Страница 3: ...723 33 STM32H725 35 and STM32H730 microcontrollers require at least one single power supply to be fully operational Additional power supplies or voltage references are required for some use cases The...

Страница 4: ...er switch Power switch Step Down Converter VCAP VSS VDDLDO VDDSMPS VLXSMPS VSSSMPS VFBSMPS VBAT VDDA VREF VREF VSSA Backup regulator VDD Backup RAM Power switch HSI CSI HSI48 HSE PLLs IOs Power switch...

Страница 5: ...Supply regulation input SMPS feedback voltage sense VSSSMPS Supply input Ground for SMPS step down converter VDDLDO Supply input Supply for the integrated low drop out regulator VCAP Supply input outp...

Страница 6: ...SS VCORE VCAP VDDLDO V reg off 5 External SMPS Supply Bypass VDD_extern VDDSMPS VLXSMPS VDD SMPS on VSSSMPS VFBSMPS VSS Ext reg VCORE 6 Bypass VCAP VDDLDO V reg off VDDSMPS VLXSMPS VDD SMPS off VSSSMP...

Страница 7: ...capacitor required VDDSMPS connected to VSS when the converter is not used 1 62 to 3 6 V VDD Four different solutions are recommended 10 F best cost trade off ESR 10m 2x 10 F best area performance tra...

Страница 8: ...output will be provided directly to the VDD33USB through the internal connection This pin is internally tied to VDD when it is not present in some specific packages In consequence the VDD supply level...

Страница 9: ...1 F 5V Two different possible use cases 3 3V Battery 100 nF VDD 100 nF 4 7 F VDD Two different possible use cases 100nF 100 nF 2 2 F LDO enabled LDO disabled VCAP3 SMPS enabled SMPS disabled 10 F 220...

Страница 10: ...either the USB VBUS or an external power supply can be used to provide the required voltage The internal regulator output supply is connected to the USB FS PHY and is also available on the VDD33USB p...

Страница 11: ...D_MIN VDD VDD VDD33USB USB functional VDDUSB_MIN Figure 5 VDD33USB connected to external power supply VDD33USB forbidden area time VDD33USB_MAX USB functional VDD33USB forbidden area VDD33USB Power on...

Страница 12: ...wer supply battery connected to the VBAT pin cannot support this current injection it is strongly recommended to connect an external low drop diode between this power supply and the VBAT pin Refer to...

Страница 13: ...aled by programming the voltage scaling VOS0 to VOS3 depending on the required performance see the reference manual STM32H723 733 STM32H725 735 and STM32H730 advanced Arm based 32 bit MCUs RM0468 In S...

Страница 14: ...ded by an external regulator After start up the SMPS can be set by software to provide a regulated output of 1 8 V or 2 5 V The external regulator must ensure the correct voltage scaling for the run a...

Страница 15: ...VPOR PDR falling edge tRSTTEMPO is approximately 377 s VPOR PDR rising edge is 1 67 V typical and VPOR PDR falling edge is 1 62 V typical Refer to the STM32H72x and STM32H73x datasheets for the actual...

Страница 16: ...3 STM32H725 735 and STM32H730 advanced Arm based 32 bit MCUs RM0468 Three BOR levels are possible 2 1 V 2 4 V 2 7 V see the STM32H72x and STM32H73x datasheets for the electrical characteristics 2 2 3...

Страница 17: ...anagement reset Figure 9 Reset circuit VDD Filter Pulse generator 20 s min RPU OR nreset System Reset NRST External reset CR RCC SFTRESET lpwr_rst wwdg1_out_rst iwdg1_out_rst pwr_por_rst pwr_bor_rst 2...

Страница 18: ...ed to generate the high frequency clocks for the system and peripherals For both the HSE and LSE the clock can also be provided from an external source using the OCS_IN and OSC32_IN pins HSE bypass an...

Страница 19: ...To RTC AWU RTCEN To IWDG1 tempo 1 2 4 8 HSION CSION HSI48ON HSIDIV HSEON SCGU System Clock Generation rcc_rtc_ck PKEU Peripheral Clock Enabling CSS LSEON pll1_r_ck traceclkin To TPIU CRS Clock recover...

Страница 20: ...face SAI DFSDM I2S When an external clock reference is needed USB_PHY External clock input USB clock provided by the external PHY The embedded PHY supports FS For HS an external PHY needs to be used E...

Страница 21: ...can use the USB SOF signal CSI 4 MHz No Low Power Internal oscillator Faster start up time than HSI Can be used for wake up from Stop mode LSI 32 KHz No Low Speed Internal clock for independent watch...

Страница 22: ...r For CL1 and CL2 use high quality ceramic capacitors in the 5 pF to 25 pF range typical designed for high frequency applications and selected to meet the requirements of the crystal or resonator CL1...

Страница 23: ...e HSI oscillator and the HSE oscillator is disabled If a failure is detected on the HSE clock this oscillator is automatically disabled a clock failure event is sent to the break inputs of the advance...

Страница 24: ...UT CONTROL VDD VSS On off Output data register Input data register To on chip peripherals To ADC Each ADC has 6 inputs optimized for high performance INP0 to INP5 and INN0 to INN5 fast channels Refer...

Страница 25: ...n the Pxy_C pads by closing the switch between the two pads 4 1 3 Package having Pxy available but nor the peer Pxy_C Closing the switch in the pad GPIOx_MODER bit connects an ADC slow input to the Px...

Страница 26: ...ress space mapped on the AXIM interface All the RAM address space ITCM DTCM RAMs and SRAMs mapped on the AXIM interface The system memory bootloader The BOOT_ADD0 BOOT_ADD1 option bytes can be modifie...

Страница 27: ...program the Flash memory using one of the following serial interfaces Table 6 STM32H723 733 STM32H725 735 and STM32H730 microcontroller bootloader communication peripherals shows the supported communi...

Страница 28: ...30 advanced Arm based 32 bit MCUs RM0468 SWJ debug port section serial wire and JTAG 6 2 1 TPIU trace port The TPIU trace port comprises four data outputs plus one clock output The number of data outp...

Страница 29: ...SWO if asynchronous trace is enabled PB3 NJTRST I JTAG test nReset PB4 6 3 2 Flexible SWJ DP pin assignment After RESET SYSRESETn or PORESETn all five pins used for the SWJ DP are assigned as dedicate...

Страница 30: ...nfigured by software Special care must be taken with the TCK SWCLK pin which is directly connected to some of the clock flip flops since it should not toggle before JTAG I O is released by the user so...

Страница 31: ...the supply loop area This is due to the fact that the supply loop acts as an antenna and therefore will become the EMI main transmitter and receiver All component free PCB areas must be filled with ad...

Страница 32: ...ls the best possible electrical margin must be reached for the two logical states and slow Schmitt triggers are recommended to eliminate parasitic states Noisy signals such as clock Sensitive signals...

Страница 33: ...ery board and the NUCLEO H723ZG and NUCLEO H725ZG Nucleo boards are good references that can be used as a basis for a specific application development Details of these boards are available on www st c...

Страница 34: ...x layer PCB stack up example are intended as examples which can be used as guide lines for a stack up evaluation and selection These stack up configurations place the GND plane adjacent to the power p...

Страница 35: ...ecommended decoupling capacitors to as many VDD VSS pairs as possible Connect the decoupling capacitor pad to the power and ground plane with a wide and short trace via This reduces the series inducta...

Страница 36: ...nal trace exceeds this trace length speed criteria then a termination should be used The trace capacitance should not exceed 20 pF at 3 3 V and 15 pF at 1 8 V The maximum signal trace inductance shoul...

Страница 37: ...PC8 SDMMC1_D0 PB9 SDMMC1_CDIR PC9 SDMMC1_D1 PC10 SDMMC1_D2 PC11 SDMMC1_D3 VDD R PU SDMMC1 R PU VDD_SD SD Card Socket CMD DAT0 DAT1 DAT2 DAT3 CLK VDD Open toggles during SD card boot Only default 3 3...

Страница 38: ...in 15 pF with overall capacitive loading including Data Address SDCLK and Control no more than 20 pF 9 4 3 Octo SPI interface Interface connectivity The Octo SPI is a specialized communication interfa...

Страница 39: ...TOSPI1 OCTOSPI2 RWDS DQSM RSTO INT GPIO GPIO Port1 Port2 PG12 OCSPI2_NCS PF4 OCSPI2_CLK OCSPI2_IO0 IO7 VDD R PU 10k VDD Octo SPI memory CK DQ 0 7 CS RESET VDD VCC optional 8 bits x8 PF5 CK 22 OCSPI2_N...

Страница 40: ...en the OCTOSPIs are disabled The multiplexed mode can be very useful for some packages where the port2 is not mapped 9 4 4 DFSDM interface The digital filter for the sigma delta modulator DFSDM is ded...

Страница 41: ...are traced using the embedded trace macrocell ETM The ETM interface is synchronous with the four data bus lines D 0 3 and the clock signal CLK Interface signals layout guidelines Reference the plane u...

Страница 42: ...8 I2C1 Touch screen or communication interface OCTOSPIM_P1 External memory USART2 Communication interface SPI1 Communication interface USB FS GPIO Remaining GPIO available LQFP100 no SMPS Audio beam...

Страница 43: ...11 Conclusion This application note must be used as reference when starting a new design with an STM32H723 33 STM32H725 35 and STM32H730 microcontroller AN5419 Conclusion AN5419 Rev 2 page 43 50...

Страница 44: ...tion and updated values of external capacitors connected to VLXSMPS in Figure 3 Power supply component layout Only one additional external inductor required to improve the overall system power consump...

Страница 45: ...BOR 16 2 2 3 Programmable voltage detector PVD 16 2 2 4 Analog voltage detector AVD 17 2 2 5 System reset 17 2 2 6 Bypass mode 17 3 Clocks 18 3 1 Introduction 18 3 1 1 HSE and LSE bypass external user...

Страница 46: ...th standard JTAG connector 30 7 Recommendations 31 7 1 Printed circuit board 31 7 2 Component position 31 7 3 Ground and power supply VSS VDD 31 7 4 Decoupling 31 7 5 Other signals 32 7 6 Unused I Os...

Страница 47: ...DFSDM interface 40 9 4 5 Embedded trace macrocell ETM 41 10 Use case examples 42 11 Conclusion 43 Revision history 44 Contents 45 List of tables 48 List of figures 49 AN5419 Contents AN5419 Rev 2 page...

Страница 48: ...Table 5 Boot modes 26 Table 6 STM32H723 733 STM32H725 735 and STM32H730 microcontroller bootloader communication peripherals 27 Table 7 TPIU trace pins 28 Table 8 External debug trigger pins 29 Table...

Страница 49: ...s for ADC1 and ADC2 24 Figure 13 Boot mode selection implementation example 27 Figure 14 Host to board connection 28 Figure 15 JTAG connector implementation 30 Figure 16 Typical layout for VDD VSS pai...

Страница 50: ...ts and ST assumes no liability for application assistance or the design of Purchasers products No license express or implied to any intellectual property right is granted by ST herein Resale of ST pro...

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