ST STM32F10 Series, Примечание к применению

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Debug management AN2586 - Application note
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4.3.2 Flexible SWJ-DP pin assignment
After reset (SYSRESETn or PORESETn), all five pins used for the SWJ-DP are assigned as
dedicated pins immediately usable by the debugger host (note that the trace outputs are not
assigned except if explicitly programmed by the debugger host).
However, the STM32F10xxx MCU implements a register to disable some part or all of the
SWJ-DP port, and so releases the associated pins for general-purpose I/Os usage. This
register is mapped on an APB bridge connected to the Cortex™-M3 system bus. This
register is programmed by the user software program and not by the debugger host.
Table 3 shows the different possibilities to release some pins.
For more details, see the STM32F10xxx reference manual, UM0306, available from the
STMicroelectronics website www.st.com.
4.3.3 Internal pull-up and pull-down on JTAG pins
The JTAG input pins must not be floating since they are directly connected to flip-flops to
control the debug mode features. Special care must be taken with the SWCLK/TCK pin that
is directly connected to the clock of some of these flip-flops.
Table 2. Debug port pin assignment
SWJ-DP pin name
JTAG debug port SW debug port
Pin
assignment
Type Description Type Debug assignment
JTMS/SWDIO I
JTAG Test Mode
Selection
I/O
Serial Wire Data
Input/Output
PA13
JTCK/SWCLK I JTAG Test Clock I Serial Wire Clock PA14
JTDI I JTAG Test Data Input - - PA15
JTDO/TRACESWO O JTAG Test Data Output -
TRACESWO if async trace
is enabled
PB3
JNTRST I JTAG Test nReset - - PB4
Table 3. SWJ I/O pin availability
Available Debug ports
SWJ I/O pin assigned
PA13 /
JTMS/
SWDIO
PA14 /
JTCK/
SWCLK
PA15 /
JTDI
PB3 /
JTDO
PB4/
JNTRST
Full SWJ (JTAG-DP + SW-DP) - reset state X X X X X
Full SWJ (JTAG-DP + SW-DP) but without
JNTRST
X X X X
JTAG-DP disabled and SW-DP enabled X X
JTAG-DP disabled and SW-DP disabled Released