Figure 39.
STDES-PFCBIDIR relays
The procedure consists of the following steps.
1.
FSM Wait
: PWM signals are in IDLE state, configured in low state, to force all the MOSFETs in off state.
The AC main voltage is already under monitoring. This state is maintained until AC main reaches a lower
AC voltage threshold (
OK_Plug_ACSource
), that is 30 V
AC
. After that, an internal timeout (
TO_IDLE
) is
activated to prevent power converter connection during the first-phase synchronization procedure. FSM
moves on to
FSM Idle
.
Figure 40.
FSM_Wait block diagram
UM2979
Startup procedure
UM2979
-
Rev 1
page 23/70
