ST SPC58NHADPT176S, Руководство пользователя

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6.2 Hyperbus interface
This paragraph describes the Hyperbus interface present on the mini module.
The SPC58NHADPT176S contains only one CS (CNS), whereas the memory device contains two CSs lines, one
for RAM and one for FLASH.
The second CS is emulated using one GPIO signal (PA[15]).
The following table shows the logic between CS/GPIO from SPC58NHADPT176S and CS0/CS1 from HyperRAM/
HyperFlash device.
Table 9. Hyperbus CS truth table
CSN GPIO CS0 CS1
0 0 1 0
0 1 0 1
1 0 1 1
1 1 0 1
The logic can be realized using the scheme of the figure below.
Figure 5. Hyperbus CS scheme
The following table describes all hardware HyperBus of the mini module, their position on PCB.
Table 10. Hyperbus interface
Symbol Description Position
U14 CMOS inverter Figure 9. Overview of SPC58NHADPT176S Rev. A mini module - Bottom - C1
IC1 TTL OR gate Figure 8. Overview of SPC58NHADPT176S Rev. A mini module - Top - B1
U13 RAM 256 Mbit Figure 8. Overview of SPC58NHADPT176S Rev. A mini module - Top - B2
UM2731
Hyperbus interface
UM2731 - Rev 1
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