
3.16
PRAM_2 faults
The PRAM controller acts as an interface between the system bus and the integrated system RAM. It converts
the protocols between the system bus and the RAM array interface. The device embeds one controller, the
PRAMC_2. For further details on the PRAM controller, refer to the SPC582Bx microcontroller reference manual
Figure 17.
PRAM faults
RGM
Error out
Reset request
reset
SRAM
Memory Array
FCCU
INTC
Interrupt request
Interrupt
Fault #74
PRAM_2
Controller
Fault #75
Set
Clear
3.16.1
Corrupted system RAM access or late-write buffer mismatch (fault #74).
In case of addressing error (for example, a write error in the RAM controller resulting in corrupted RAM access),
the PRAM controller detects this fault, and it forwards it to the FCCU.
The user cannot inject this fault.
3.16.2
EDC after ECC for system RAM (fault #75).
The EDC after ECC detects faults affecting the ECC logic of the PRAM controller and forwards it to the FCCU.
The user cannot inject this fault.
3.17
TCU faults
The device monitors the signals that are part of the TCU. These signals can move the device into test mode. Test
mode, however, must not be enabled while the application runs. For this reason, if a random event asserts one of
these signals the fault is detected and forwarded to the FCCU.
A different FCCU channel monitors each diagnostic function test domain.
AN5752
PRAM_2 faults
AN5752
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Rev 1
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