
The user can inject this fault by:
1.
Enabling EOUT control by FCCU (FCCU_CFG[FCCU_SET_AFTER_RESET] = 0x1);
2.
Asserting the EOUT / EIN loopback (SIUL2_MSCR_IO27[SSS] = 0x5);
3.
Driving the EOUT to logic 0 (FCCU_CFG [FCCU_SET_CLEAR] = 0x1). Assuming the fault configured as
HW recoverable fault, the user can clear the fault by:
4.
De-asserting the EOUT / EIN loopback (SIUL2_MSCR_IO27[SSS] = 0x0);
5.
Switching back the EOUT control to the FCCU (FCCU_CFG [FCCU_SET_CLEAR] = 0x0);
6.
Re-asserting the EOUT / EIN loopback (SIUL2_MSCR_IO27[SSS] = 0x5). The FCCU error reaction path is
verified if the FCCU_RF_S3[RFS0] status bit is set after the step (3).
3.5
DMA faults
The eDMA controller is a module capable of performing complex data transfers with minimal intervention of a host
processor. For further details on the eDMA, refer to device SPC582Bx reference manual
Figure 8.
DMA faults
RGM
Error out
Reset request
reset
EDC after ECC
FCCU
INTC
Interrupt request
Interrupt
Fault #15
Set
Clear
TCD RAM
Fault #48
Fault #10
Fault #14
3.5.1
DMA_1 gasket monitor (fault #10)
In case of hardware fault results in a wrong frequency conversion between the XBAR and the DMA_1, the
hardware forwards the event to the FCCU.
The user cannot inject this fault.
3.5.2
DMA_1 ECC error (fault #14)
The ECC logic detects single bit error or double bits error and forwards this fault to the FCCU.
The user cannot inject this fault.
3.5.3
DMA_1 TCD EDC after ECC (fault #15)
The EDC after ECC logic detects a hardware fault in the ECC logic resulting in a corrupted ECC correction and
forwards this fault to the FCCU.
The user cannot inject this fault.
3.5.4
DMA_1 TCD RAM feedback error (fault #48)
If the latched control signals do not match with the ones originally sent to DMA_1 TCD RAM, the HW feedback
checker forwards this fault to the FCCU.
The user can inject this fault by the FCCU fake fault interface.
AN5752
DMA faults
AN5752
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Rev 1
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