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Circuit Description
ECL LOGIC BOARD
The ECL Logic Board contains the discriminator,
high speed counters, and bin clock generator. 8
bits of count data can be provided every 40 ns to
the TTL Logic Board for storage in data acquisition
memory.
SIGNAL INPUT
The signal input passes through the signal amplifi-
er. The amplifier has a DC to 25o MHz bandwidth
and a gain of 5 over an input range of ±300 mV.
The inputs are protected to ±5VDC and ±50V tran-
sients.
R102, R103, R104, P101, D101, D102, and D103
comprise an overload protection circuit which
clamps the amplifier input to ±350mV. AC gain is
provided by Q101 and Q102 and is compensated
by C104. U101 sets the DC gain. Q102 sums the
AC and DC signals and can drive its100Ω output
to ±2V. U102, D105, and Q103 provide a tempera-
ture compensated bias voltage for the overload
protection circuits which is adjusted by P101 to
null the DC offset at the input.
DISCRIMINATORS
Comparator U202 discriminates the amplified sig-
nal into ECL levels. The threshold is provided by
analog voltage SIGLVL and buffered by U201A.
The output transistor, Q202, provides a high fre-
quency, low impedance output. The comparator is
operated in the Schmitt trigger configuration with
about 20 mV of hysteresis. Since the input signal
has been amplified by 5, this represents about 4
mV of hysteresis at the input. Control signal
SIG_POL sets the polarity of the output at U205A.
Q204 and Q205 drive the discriminatory output.
There is a delay line between the this output and
the front panel BNC connector. This delay com-
pensates for the delay in the counter front end.
Thus DISC output pulses overlap the BIN CLK of
the bin in which the pulse is counted.
U203 is the trigger discriminator. It operates like
the signal discriminator except that is has about 75
mV of hysteresis and no gain in front of it.
U204 is the discriminator for the external bin clock
input. The threshold is fixed at 1.3V to trigger TTL
pulses. The hysteresis is also about 75 mV.
200 MHZ CLOCK AND TRIGGER SYNC
U301A is a 200 MHz LC tank oscillator. U302 di-
vides the oscillator output by 64 to provide a 3.125
MHz signal to the phase comparator U304. A 25
MHz crystal oscillator, divided by 8 in U306, is the
reference signal for U304. The output of the phase
comparator is filtered and integrated by U305 to
drive the frequency control input of the 200 MHz
oscillator, D301. The net result is a 200 MHz, crys-
tal based time base available from U301C.
The discriminated trigger input clocks latch
U311A. The latched trigger is input to U309A and
U309B. U309A is clocked by the 200 MHz clock
and U309B is clocked by the inverted 200 MHz.
U310 allows whichever flip-flop clocks first to lock
out the other. U308D then outputs a 200 MHz
clock which has at most 2.5 ns of indeterminacy
with respect to the trigger. The output of U308D is
then the master clock for this trigger. U311B di-
vides the clock to 100 MHz and U313B divides to
50 MHz. Q303 and Q304 provide the 50 MHz
TEST signal. When all of the bins for the record
have been generated, the signal DONE_ECL re-
sets U311A and U311B which disables the clocks.
This turns off the BIN CLK output and TEST out-
put.
BIN CLOCK GENERATOR
When the bins clocks are being generated inter-
nally, the 100 MHz output of U311B feeds a divid-
er chain made up of U402AB, U403AB, U404A,
and U412. U402, U403, and U404 are ECL flip-
flops which divide by 2. They are enabled by con-
trol lines B0 - B3 to provide divide by 2,4,8,16, or
32. U412 is a TTL divider which can divide by 2
through 2^15 by programming the A-D inputs. The
input to U412 is 6.25 MHz and the last output of
U412 can be as low as 1906.7 Hz. The divider out-
puts are combined in U407B to give an output
pulse which is synchronous with the 100 MHz
clock and lasts for 10 ns. The output of U407B has
a frequency range from 50 MHz to 1906.7 Hz in bi-
nary steps.
U404B divides this frequency by 2. U405AB di-
vides the frequency by 2 again and provides 4 out-
puts which are 90 degrees apart in phase.
U406AB synchronize these outputs with the 100
MHz clock once again. At the highest frequency,
the output of U406 will be 12.5 MHz which is the
bin clock for 40 ns bins. Each half cycle of the out-
put clock is a 40 ns count bin for a total period of
80 ns or 12.5 MHz. The 4 quadrature signals are
combined in U410 to provide signals to reset the
counters, latch the count data, write the data to
memory, etc. These signals are synchronous with
the count bins.