2.5
Status Model
2 – 21
This register is cleared at power-on.
2.5.7
Overload Status (OVCR)
The Overload Condition Register consists of 5 single-bit monitors of
conditions within the SIM980. Bits in the OVCR reflect the real-time
values of their corresponding signals. Reading the entire register, or
individual bits within it, does not a
ff
ect the OVCR.
Weight
Bit
Flag
1
0
Overload Channel 1
2
1
Overload Channel 2
4
2
Overload Channel 3
8
3
Overload Channel 4
16
4
Overload Output
32
5
undef (0)
64
6
undef (0)
128
7
undef (0)
Overload Channel
n
: The input bu
ff
er for Channel
n
is overloaded (input voltage
exceeds
±
10 V). Note that the overload detection is active even
if the channel is o
ff
.
Overload Output : The output of the summing amplifier is overloaded (output
voltage exceeds
±
10 V). Note that the output can overload with-
out any input channel overloading, and vice versa.
2.5.8
Overload Status (OVSR)
The Overload Status Register consists of (latching) event flags that
correspond one-to-one with the bits of the OVCR (see above). Upon
the transition 0
→
1 of any bit within the OVCR, the corresponding
bit in the OVSR becomes set.
Bits in the OVSR are una
ff
ected by the 1
→
0 transitions in the OVCR,
and are cleared only by reading or with the
*CLS
command. Reading
a single bit (with the
OVSR?
i
query) clears only bit
i
.
2.5.9
Overload Status Enable (OVSE)
The OVSE acts as a bitwise AND with the OVSR register to produce
the single bit OVSB message in the Status Byte Register (SB). It can
be set and queried with the
OVSE(?)
command.
This register is cleared at power-on.
SIM980
Analog Summing Amplifier