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(c) Spectrum Instrumentation GmbH
Trigger
Mode Gated Sampling
Detailed description of the logic gate trigger modes
Positive TTL edge trigger
This mode is for detecting the rising edges of an external TTL sig
-
nal. The gate will start on rising edges that are detected after start
-
ing the board.
As this mode is purely edge-triggered, the high level at the cards
start time, does not trigger the board.
With the next falling edge the gate will be stopped.
HIGH TTL level trigger
This mode is for detecting the high levels of an external TTL signal.
The gate will start on high levels that are detected after starting
the board acquisition/generation.
As this mode is purely level-triggered, the high level at the cards
start time, does trigger the board.
With the next low level the gate will be stopped.
Negative TTL edge trigger
This mode is for detecting the falling edges of an external TTL sig
-
nal. The gate will start on falling edges that are detected after
starting the board.
As this mode is purely edge-triggered, the low level at the cards
start time, does not trigger the board.
With the next rising edge the gate will be stopped.
SPC_TRIG_CH0_LEVEL0
42200
read/write
Set it to the desired trigger level in mV
mV
SPC_TRIG_CH0_PULSEWIDTH
44101
read/write
Sets the pulsewidth in samples. Values from 2 to [4G - 1] are allowed.
2 to [4G - 1]
Register
Value
Direction
set to
Value
SPC_TRIG_EXT1_MODE
SPC_TRIG_EXT2_MODE
SPC_TRIG_EXT3_MODE
40511
40512
40513
read/write
SPC_TM_POS
1h
Register
Value
Direction
set to
Value
SPC_TRIG_EXT1_MODE
SPC_TRIG_EXT2_MODE
SPC_TRIG_EXT3_MODE
40511
40512
40513
read/write
SPC_TM_HIGH
8h
Register
Value
Direction
set to
Value
SPC_TRIG_EXT1_MODE
SPC_TRIG_EXT2_MODE
SPC_TRIG_EXT3_MODE
40511
40512
40513
read/write
SPC_TM_NEG
2h
Register
Value
Direction
set to
Value
Содержание M2p.59 Series
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