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telemetry channels within the specific frequency band can be
received. This PCBA demodulates the RF signal and passes on low
level PWM to the digital PCBA. The digital PCBA conditions the
PWM signal and provides frame synchronization. After ensuring that
valid data is present, the digital PCBA passes the PWM data to the
CPU PCBA where the PWM is demodulated into vital signs patient
data and processed.
CPU (80C186) PCBA Description
The CPU PCBA consists of the following major features (refer to
•
256 KB of static RAM and 256 KB of ROM.
•
RAM and ROM are organized as 128 kwords × 16 bits.
•
EEPROM memory and static RAM hold arrhythmia, NeoTrend,
and configuration data.
•
Primary data control for the 90478 modules.
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Provides control functions for ECG PCBA (via 448CNTRL).
Watchdog/Power Reset
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Re-triggerable one-shot timed to generate a 1.1-second pulse.
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Resets CPU if software does not re-trigger within 1.1 seconds.
•
After module insertion, keeps CPU and RUPI reset until +5 volts
stabilizes.
SDLC Mainframe Interface
•
SDLC data and clock signals are routed from the rear connector
to the SDLC transceiver circuit.
•
The transceiver circuit converts the differential bus signals to the
on-board CMOS logic levels (0 to +5 volts) and provides
directional control for the two-way DATA lines.
•
SDLC CLOCK: 1.892352 MHz generated by mainframe remote
universal peripheral interface (RUPI).
•
SDLC DATA lines route data between the mainframe and the
module CPU.
•
Clock signal routed to the RUPI to synchronize SDLC
communications.
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SDLC clock is used as a source for 448 Hz interrupt.
•
RUPI runs in polled mode.
