68
WX-7700MDX
*1 Loading motor (M903) control
LOAD (pin
6
)
“L”
“H”
“L”
“H”
EJECT (pin
7
)
“L”
“L”
“H”
“H”
Terminal
Operation
STOP
LODING
EJECT
BRAKE
Pin No.
Pin Name
I/O
Description
44
EE-SIO
I/O
Two way data bus with the external EEPROM device Not used
45
MD-SO
O
Writing serial data signal output to the CXD2662R and CXA2523AR
46
LINKOFF
O
Unilink on/off control signal output for the SONY bus interface “L”: link on, “H”: link off
Not used
47
UNIREQ
O
Data request signal output terminal (for SONY bus) “H”: request on Not used
48
UNICKIO
I/O
Serial clock signal input from the master controller
49
UNISI
I
Serial data input from the SONY bus interface
50
UNISO
O
Serial data output to the SONY bus interface
51
MD-CKO
O
Serial data transfer clock signal output to the CXD2662R and CXA2523AR
52
MD-SI
I
Reading serial data signal input from the CXD2662R
53
NCO
O
Not used
54
SENS
I
Internal status (SENSE) input from the CXD2662R
55
CC-XINT
I
Interrupt status input from the CXD2662R
56
LIMIT-IN
I
Detection input from the MD sled limit-in detect switch
The optical pick-up is inner position when “L”
57
EJT-KEY
I
Front panel status signal input terminal “H”: front panel full open Not used
58
ERROR-PWM
O
PWM error monitor output terminal (C1error rate and ATER is output when test mode)
Not used
59
MD-RST
O
Reset signal output to the CXD2662R and BH6518FS “L”: reset
60
BU-IN
I
Back-up power supply detect signal input from the SONY bus interface
“L” is input at low voltage
61
BUS-ON
I
SONY bus on/off control signal input from the master controller “L”: bus on
62
SQSY
I
Subcode Q sync (SCOR) input from the CXD2662R
“L” is input every 13.3 msec Almost all, “H” is input
63
C-SW
I
Inputs a MD disc loading start or a MD disc eject completion detect switch detection signal
“L”: When loading start or eject completed of a disc loading operation
64
MD-LAT
O
Serial data latch pulse signal output to the CXD2662R and CXA2523AR
65
MD-ON
O
Power supply on/off control signal output of the MD mechanism deck section main power supply
“H”: power on
66
DEEMP
O
MD emphasis control signal output to the master controller “H”: emphasis on
67
A-ATT
O
Audio line muting on/off control signal output “H”: muting on
68
NCO
O
Not used
69
TSTCKO
O
Output of clock signal for the test mode display Not used
70
TSTSO
O
Output of data for the test mode display Not used
71
TSTMOD
I
Setting terminal for the test mode “L”: test mode, “H”: normal mode
72
VDD
—
Power supply terminal (+5V)
73
NIL
I
Not used
74 to 77
TOUT0 to TOUT3
O
In test mode, output of the 4x8 matrix test keys Not used
78 to 80
TIN0 to TIN2
I/O
In test mode, input of the 4x8 matrix test key In nomal mode, output “L” Not used