Sony SCD-XA9000ES - Es Super Audio Cd Player, Руководство по обслуживанию

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SCD-XA9000ES
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MAIN BOARD IC801 CXD2753R (DSD DECODER)
Pin No. Pin Name I/O Description
1 VSCA0 — Ground terminal (for core)
2 XMSLAT I
Serial data latch pulse signal input from the CPU
3 MSCK I
Serial data transfer clock signal input from the CPU
4 MSDATI I Serial data input from the CPU
5 VDCA0 —
Power supply terminal (+2.5V) (for core)
6 MSDATO O
Serial data output to the CPU
7 MSREADY O Ready signal output to the CPU “L”: ready
8 XMSDOE O
Serial data output enable signal output terminal Not used
9 XRST I
Reset signal input from the I/O expander “L”: reset
10 SMUTE I Soft muting on/off control signal input from the CPU “H”: muting on
11 MCKI I
Master clock signal (33.8688 MHz) input terminal
12 VSIOA0 —
Ground terminal (for I/O)
13 EXCKO1 O External clock 1 signal output terminal Not used
14 EXCKO2 O
External clock 2 signal output terminal Not used
15 LRCK O
L/R sampling clock signal (44.1 kHz) output terminal Not used
16 F75HZ O Not used
17 VDIOA0 —
Power supply terminal (+3.3V) (for I/O)
18 to 25 MNT0 to MNT7 O
Monitor signal output terminal Not used
26 TCK I
Clock signal input terminal for the test (normally: fixed at “L”)
27 TDI I
Input terminal for the test (normally: open)
28 VSCA1 —
Ground terminal (for core)
29 TDO O
Output terminal for the test (normally: open)
30 TMS I
Input terminal for the test (normally: open)
31 TRST I
Reset terminal for the test (normally: fixed at “L”)
32 to 34 TEST1 to TEST3 I
Input terminal for the test (normally: fixed at “L”)
35 VDCA1 — Power supply terminal (+2.5V) (for core)
36 UBIT O
Monitor terminal relative to DST Not used
37 XBIT O
Monitor terminal relative to DST Not used
38 to 41
SUPDT0 to
SUPDT3
O
Supplementary data output terminal Not used
42 VSIOA1 —
Ground terminal (for I/O)
43, 44
SUPDT4, SUPDT5
O
Supplementary data output terminal Not used
45 VDIOA1 — Power supply terminal (+3.3V) (for I/O)
46, 47
SUPDT6, SUPDT7
O
Supplementary data output terminal Not used
48 SUPEN O
Supplementary data enable signal output terminal Not used
49 VSCA2 — Ground terminal (for core)
50 DSAEXR O
Not used
51, 52 TEST4, TEST5 I
Input terminal for the test (normally: fixed at “L”)
53 NC O Not used
54 VDCA2 —
Power supply terminal (+2.5V) (for core)
55 DSADML O
DSD data output terminal for L-ch down mix Not used
56 DSADMR O DSD data output terminal for R-ch down mix Not used
57 BCKASL I
Input/output selection signal input terminal of bit clock signal (2.8224 MHz) for DSD data output
“L”: input (slave), “H”: output (master) Fixed at “L” in this set
58 VSDSD0 —
Ground terminal (for DSD data output)
59 BCKAI I Clock signal (5.6448 MHz) input terminal