Sony MEX-N5100BE, Руководство по обслуживанию

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MEX-N5100BE/N5100BT/N5150BT
42
MAIN BOARD IC705 TC94A99FG-003 (SYCH (RF AMP, DIGITAL SERVO PROCESSOR, AUDIO DSP)
Pin No. Pin Name I/O Description
1 LPFO O PLL circuit low-pass fi lter ampli fi er output terminal
2 PVREF - PLL circuit reference voltage (+1.65V) terminal
3 VCOF O VCO fi lter terminal
4 RVSS3 - Ground terminal
5 VCOI I DSP VCO control voltage input terminal
6 RVDD3 - Power supply terminal (+3.3V)
7 SLCO O EFM slice level output terminal
8 RFI I RF signal input terminal
9 RFRPI I RF ripple signal input terminal
10 RFEQO O RF equalizer circuit output terminal
11 DCOFC O RF equalizer offset compensation low-pass fi lter output terminal
12 AGCI I RF signal auto gain control ampli fi er input terminal
13 RFO O RF signal generation ampli fi er output terminal
14 RVSS3 - Ground terminal
15 FNI2 I Main beam (B) input from the CD mechanism deck block
16, 17 FNI1, FPI2 I Main beam (C) input from the CD mechanism deck block
18 FPI1 I Main beam (A) input from the CD mechanism deck block
19 VDD1_1 - Power supply terminal (+1.5V)
20 TPI I Sub beam (F) input from the CD mechanism deck block
21 TNI I Sub beam (E) input from the CD mechanism deck block
22 VRO O Reference voltage (+1.65V) output to the CD mechanism deck block
23 AVSS3 - Ground terminal
24 MDI I Laser power detection signal input from the CD mechanism deck block
25 LDO O Laser power control signal output to the CD mechanism deck block
26 FSMONIT O Not used
27 RFZI I RF ripple zero-cross signal input terminal
28 RFRP O RF ripple signal output terminal
29 TEI O Tracking error signal output terminal
30 AVDD3 - Power supply terminal (+3.3V)
31 FOO O Focus coil control signal output to the CD mechanism deck block
32 TRO O Tracking coil control signal output to the CD mechanism deck block
33 VSS_1 - Ground terminal
34 FMO O Sled motor control signal output to the CD mechanism deck block
35 DMO O Spindle motor control signal output to the CD mechanism deck block
36 VDDM1 - Power supply terminal (+1.5V)
37 SRAMSTB I Standby signal input from the system controller “L”: standby
38 VDD1_2 - Power supply terminal (+1.5V)
39 VDD3_1 - Power supply terminal (+3.3V)
40, 41
PIO10/CDMON2,
PIO11/CDMON3
I/O Not used
42 PIO12 I Audio data input from the system controller
43 PIO13 I Bit clock signal input from the pin 49 (PIO19)
44 PIO14 I L/R sampling clock signal input from the pin 48 (PIO18)
45 PIO15 O Audio data output to the system controller
46, 47 PIO16, PIO17 I/O Not used
48 PIO18 O L/R sampling clock signal output to the system controller
49 PIO19 O Bit clock signal output to the system controller
50 PIO20 I/O Not used
51 DVDD12 - Power supply terminal (+3.3V)
52 DAO1 O Audio signal (rear R-ch) output to the electrical volume
53 DVSS12 - Ground terminal
54 DAO2 O Audio signal (front R-ch) output to the electrical volume
55 DVREF - Reference voltage terminal
56 DVDD34 - Power supply terminal (+3.3V)
57 DAO3 O Audio signal (front L-ch) output to the electrical volume
58 DVSS34 - Ground terminal
59 DAO4 O Audio signal (rear L-ch) output to the electrical volume
60 DVDD5 - Power supply terminal (+3.3V)