HCD-VX888
25
25
6-3.
BLOCK DIAGRAM – DISPLAY/POWER Section –
IC504
IC504
E
G
C
B
TUNER/CD
SECTION
(Page 23)
F
DISPLAY/POWER
SECTION
(Page 26)
IC101
L. P. F.
MAIN
SECTION
(Page 24)
MAIN
SECTION
(Page 24)
TUNER/CD
SECTION
(Page 23)
: VIDEO
• Signal Path
• R-ch is omitted due to same as L-ch.
: CD
VIDEO CD CONTROL
IC502 (2/2)
3
RESOLUTION
4
CHROMA LEVEL
22
BGP
36
DATAI
35
DATAO
88
DF LATCH
37
CLK1
21
H SYNC IN
BUFFER
20
CL680 INTERRUPT
45
V SYNC
BUFFER
87
CL680 HSEL
85
CL680 HRDY
86
680 RESET
65
V.MUTING
HD OUT
112
HD IN
119
HCK
117
H SYNC
101
V SYNC
93
HINT
114
HSEL
121
HRDY
113
RESET
60
CD DATA
4
CD BCK
3
CD LRCK
5
CD C2PO
6
VIDEO SIGNAL PROC.
MPEG VIDEO/AUDIO DECODER
IC505
MD
9
MC
8
ML
7
DATA
18
BCK
17
LRCK
19
384FSO
20
MCKO
4
111
110
DA DATA
DA BCK
86
DA XCLK
106
VCK IN
75
C OUT
D/A CONV
DIGITAL FILTER
IC509
108
DA LRCK
27MHz
RSTB
10
14
V OUT L
11
V OUT R
1
XT1
24
XT2
R-CH
X503
27MHz
X501
10MHz
LOUT
L.P.F
VIN
1
BGP
5
6
VOUT
C AMP
IC302
TINT
8
VIN
10
CCT
5
1
VOUT
Y AMP
IC303
69
Y OUT
CD DATA/CD BCK/CD LRCK/C2PO
S VIDEO
OUT
J301
4
3
2
1
Y IN
2
C IN
7
MUTE A
1
MUTE B
8
Y/C DECODER
IC304
15
Y OUT1
9
C OUT
12
MIX OUT1
11
MIX OUT2
14
Y OUT2
MD0
MD15
54
52
50
48
.
46
58
56
.
.
44
17
19
21
.
23
.
10
15
.
29
.
.
MA0
MA10
16
19
22
26
.
DQ1
DQ16
A0
A8
RAS
14
UCAS
28
LCAS
29
WE
13
DRAM
IC507
O0
O7
A0
A10
CE
22
ROM
IC510
12
5
27
.
26
23
.
.
17
21
25
.
4
.
13
15
.
28
29
3
.
.
2
30
.
.
.
42
RAS0
40
CAS
38
MWE
37
MCE
Q301
C
Y
7
10
31
.
34
.
2
5
.
36
39
66
32
33
34
31
12
9
46
41
DAC RESET
DATA1I
CLK1
RTS1
DATA1O
XRESET
CNVSS
BUS XWRL
BUS XHOLD
TXD
SCLK
BUSY
RXD
RST
XRST
PGM
XWR
HOLD
7
5
L.P.F
MCLK
A11
ı
A17
15
13
XIN
XOUT
Q501
Q502
Q531
+3.3V REG
+3.3V
(IC505 VDD)
+5V
VMP-VIDEO IN
CN503
(TO FLASH WRITER)
11
10
9
8
3
4
5
6
w w w . x i a o y u 1 6 3 . c o m
Q Q 3 7 6 3 1 5 1 5 0
9
9
2
8
9
4
2
9
8
T E L
1 3 9 4 2 2 9 6 5 1 3
9
9
2
8
9
4
2
9
8
0
5
1
5
1
3
6
7
3
Q
Q
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