HCD-MX500i/MX550i
49
BD96U BOARD IC401 92CD28AFG-7FU8 (M (USB CONTROLLER)
Pin No.
Pin Name
I/O
Description
1
USB-RST
I
Reset signal input from the system controller “L”: reset
2
I-USB-DI
I
Ready to send signal input from the system controller
3, 4
INT1, INT2
O
Not used
5
INT3
I
Function selection signal input terminal Fixed at “H” in this set
6
DVCC3B
-
Power supply terminal (+3.3V)
7 to 9
XT1, XT2, PWE
-
Not used
10
DVSS1B
-
Ground terminal
11
DVCC1B
-
Power supply terminal Not used
12
RVOUT1
O
Reference voltage (+3.3V) output terminal Not used
13, 14
RVIN
I
Reference voltage (+3.3V) input terminal
15
RVOUT2
O
Reference voltage (+3.3V) output terminal Not used
16
DVCC1A
-
Power supply terminal Not used
17
DVSS1A
-
Ground terminal
18 to 25
D0 to D7
I/O
Two-way data bus with the S-RAM
26
DVSS
-
Ground terminal
27
DVCC3A
-
Power supply terminal (+3.3V)
28 to 35
D8 to D15
I/O
Two-way data bus with the S-RAM
36
A0
O
Address signal output terminal Not used
37 to 43
A1 to A7
O
Address signal output to the S-RAM
44
DVSS
-
Ground terminal
45
DVCC3A
-
Power supply terminal (+3.3V)
46 to 54
A8 to A16
O
Address signal output to the S-RAM
55 to 58
BUS0-U to BUS3-U
O
Serial data output to the CD-MP3 processor
59
BUCK-U
O
Serial data transfer clock signal output to the CD-MP3 processor
60
CCE-U
O
Chip enable signal output to the CD-MP3 processor
61
A23
O
Not used
62
DVSS
-
Ground terminal
63
DVCC3A
-
Power supply terminal (+3.3V)
64
RD
O
Output enable signal output to the S-RAM
65
SRWR
O
Write enable signal output to the S-RAM
66
SRLLB
O
Lower-byte control signal output to the S-RAM
67
SRLUB
O
Upper-byte control signal output to the S-RAM
68
TA0IN
O
Not used
69
BOOT
I
Boot mode selection signal input terminal “L”: boot mode
70
SRAM-CS
O
Chip select signal output to the S-RAM
71
LRCK
O
L/R sampling clock signal output to the CD-MP3 processor
72
AM1
I
Function mode selection signal input terminal Fixed at “H” in this set
73
X2
O
System clock output terminal (9 MHz)
74
DVSS
-
Ground terminal
75
X1
I
System clock input terminal (9 MHz)
76
DVCC3A
-
Power supply terminal (+3.3V)
77
USBOC
I
Over current detection signal input terminal
78
USBPON
O
USB VBUS power on/off control signal output terminal “H”: power on
79
D+
I/O
Two-way data (positive) bus with the USB connector
80
D-
I/O
Two-way data (negative) bus with the USB connector
81
AM0
I
Function mode selection signal input terminal Fixed at “H” in this set
82
X1USB
O
Not used
83
DVSS
-
Ground terminal
84
O-USB-DO
O
Clear to send signal output to the system controller
85
DATA
I
Audio data input from the CD-MP3 processor
86
CLK
I
Audio data transfer clock signal input from CD-MP3 processor
87
O-USB-SO
O
Serial data output to the system controller
88
I-USB-SI
I
Serial data input from the system controller
89
SPCLK
-
Not used
90
SO0
-
Not used
91
SI0
-
Not used
92
BCK
O
Bit clock signal output to the CD-MP3 processor
93
A-IN
O
Audio data output to the CD-MP3 processor
