Sony HCD-BC150 - Dvd Home Theater System, Руководство по обслуживанию

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63
HCD-BC150/BC250
• MAIN BOARD IC506 CXD9720BQ (DIGITAL AUDIO PROCESSOR)
Pin No. Pin Name I/O Description
1 VSS — Ground terminal
2 XRST I System reset signal input from the system controller “L”: reset
3 EXTIN I Master clock signal input terminal Not used
4 LRCKI3 I L/R sampling clock signal input terminal Not used
5 VDDI — Power supply terminal (+2.6V)
6 BCKI3 I Bit clock signal input terminal Not used
7 PLOCK O Internal PLL lock signal output terminal Not used
8 VSS — Ground terminal
9 MCLK1 I System clock input terminal (13.9 MHz)
10 VDDI — Power supply terminal (+2.6V)
11 VSS — Ground terminal
12 MCLK2 O System clock output terminal (13.9 MHz)
13 MS I
Master/slave setting terminal “L”: internal clock, “H”: external clock
Fixed at “L” in this set
14 SCKOUT O Internal system clock output to the D/A converter
15 LRCKI1 I L/R sampling clock signal input from the digital audio interface receiver
16 VDDE — Power supply terminal (+3.3V)
17 BCKI1 I Bit clock signal input from the digital audio interface receiver
18 SDI1 I Audio serial data input from the A/D converter
19 LRCKO O L/R sampling clock signal output to the D/A converter
20 BCKO O Bit clock signal output to the D/A converter
21 VSS — Ground terminal
22 KFSIO I Audio clock signal input from the digital audio interface receiver
23 to 25 SDO1 to SDO3 O Audio serial data output to the D/A converter
26 SDO4 O Audio serial data output terminal Not used
27 SPDIF O SPDIF signal output terminal Not used
28 LRCKI2 I L/R sampling clock signal input from the digital audio interface receiver
29 BCKI2 I Bit clock signal input from the digital audio interface receiver
30 SDI2 I Audio serial data input from the digital audio interface receiver
31 VSS — Ground terminal
32 HACN O Acknowledge signal output to the system controller
33 HDIN I Serial data input from the system controller
34 HCLK I Serial data transfer clock signal input from the system controller
35 HDOUT O Serial data output to the system controller
36 HCS I Chip select input from the system controller
37 GP12 I Write signal input from the system controller
38 GP13 O SD-RAM chip enable output terminal Not used
39 GP14 O Row address strobe signal output terminal Not used
40 VDDI — Power supply terminal (+2.6V)
41 VSS — Ground terminal
42 GP15 O Column address strobe signal output terminal Not used
43 OE0 O Output terminal of data input/output mask Not used
44 CS0 O Chip select signal output to the S-RAM
45 WE0 O Write enable signal output to the S-RAM
46 VDDE — Power supply terminal (+3.3V)
47 WMD1 I External memory wait mode setting terminal Fixed at “H” in this set
48 VSS — Ground terminal