Specifications
FCB-EH6500(GB) A-EEP-100-11(1)
LVDS receiver circuit example (Single output)
D
3
.
3
V
_
C
N
6
0
1
3
0
P
1
T
X
O
U
T
4
-
2
T
X
O
U
T
4
+
3
T
X
O
U
T
5
-
4
T
X
O
U
T
5
+
5
R
E
S
E
T
6
N
C
7
T
X
O
U
T
6
-
8
T
X
O
U
T
6
+
9
T
X
O
U
T
7
-
1
0
T
X
O
U
T
7
+
1
1
G
N
D
1
2
G
N
D
1
3
U
N
R
E
G
1
4
U
N
R
E
G
1
5
U
N
R
E
G
1
6
U
N
R
E
G
1
7
U
N
R
E
G
1
8
R
X
D
1
9
T
X
D
2
0
G
N
D
2
1
T
X
O
U
T
0
-
2
2
T
X
O
U
T
0
+
2
3
T
X
O
U
T
1
-
2
4
T
X
O
U
T
1
+
2
5
T
X
O
U
T
2
-
2
6
T
X
O
U
T
2
+
2
7
T
X
C
L
K
O
U
T
-
2
8
T
X
C
L
K
O
U
T
+
2
9
T
X
O
U
T
3
-
3
0
T
X
O
U
T
3
+
R
E
S
E
T
C
6
0
1
1
0
u
2
5
V
R
X
D
C
6
0
2
0
.
1
u
2
5
V
C607
0.1u
25V
R
6
0
2
1
0
0
U
N
R
E
G
R
6
0
4
1
0
0
T
X
D
FB602
R
6
0
1
1
0
0
R
6
0
3
1
0
0
R
6
0
5
1
0
0
I
C
6
0
1
T
H
C
6
3
L
V
D
1
0
2
4
-
1
L
T
N
1
PGND_1
2
PVCC_2
3
RESERVED
4
PDWN
5
MODE0
6
MODE1
7
DK
8
R/F
9
OE
10
MODE2
11
MAP
12
VCC_12
13
GND_13
14
R20
15
R21
16
R22
17
R23
18
R24
19
R25
20
R26
21
VCC_21
22
GND_22
23
R27
24
R28
25
R29
26
G20
27
G21
28
VCC_28
29
VCC_29
30
GND_30
31
G22
32
G23
33
G24
34
G25
35
G26
36
G27
3
7
G
2
8
3
8
V
C
C
_
3
8
3
9
G
N
D
_
3
9
4
0
G
2
9
4
1
B
2
0
4
2
B
2
1
4
3
B
2
2
4
4
B
2
3
4
5
B
2
4
4
6
V
C
C
_
4
6
4
7
G
N
D
_
4
7
4
8
B
2
5
4
9
B
2
6
5
0
B
2
7
5
1
B
2
8
5
2
B
2
9
5
3
V
C
C
_
5
3
5
4
G
N
D
_
5
4
5
5
C
O
N
T
2
1
5
6
C
O
N
T
2
2
5
7
V
C
C
_
5
7
5
8
G
N
D
_
5
8
5
9
G
N
D
_
5
9
6
0
C
L
K
O
U
T
6
1
C
V
C
C
6
2
C
G
N
D
6
3
R
1
0
6
4
R
1
1
6
5
R
1
2
6
6
R
1
3
6
7
R
1
4
6
8
R
1
5
6
9
R
1
6
7
0
V
C
C
_
7
0
7
1
G
N
D
_
7
1
7
2
R
1
7
73
R18
74
R19
75
G10
76
G11
77
G12
78
G13
79
G14
80
VCC_80
81
GND_81
82
G15
83
G16
84
G17
85
G18
86
G19
87
B10
88
VCC_88
89
GND_89
90
B11
91
B12
92
B13
93
B14
94
B15
95
B16
96
B17
97
VCC_97
98
GND_98
99
B18
100
B19
101
HSYNC
102
VSYNC
103
DE
104
CONT11
105
CONT12
106
VCC_106
107
PVCC_107
108
PGND_108
1
0
9
L
G
N
D
_
1
0
9
1
1
0
R
A
1
-
1
1
1
R
A
1
+
1
1
2
R
B
1
-
1
1
3
R
B
1
+
1
1
4
L
V
C
C
_
1
1
4
1
1
5
L
G
N
D
_
1
1
5
1
1
6
R
C
1
-
1
1
7
R
C
1
+
1
1
8
R
C
L
K
-
1
1
9
R
C
L
K
+
1
2
0
L
V
C
C
_
1
2
0
1
2
1
L
G
N
D
_
1
2
1
1
2
2
R
D
1
-
1
2
3
R
D
1
+
1
2
4
R
E
1
-
1
2
5
R
E
1
+
1
2
6
L
V
C
C
_
1
2
6
1
2
7
L
G
N
D
_
1
2
7
1
2
8
R
A
2
-
1
2
9
R
A
2
+
1
3
0
R
B
2
-
1
3
1
R
B
2
+
1
3
2
L
V
C
C
_
1
3
2
1
3
3
L
G
N
D
_
1
3
3
1
3
4
R
C
2
-
1
3
5
R
C
2
+
1
3
6
L
G
N
D
_
1
3
6
1
3
7
L
G
N
D
_
1
3
7
1
3
8
L
V
C
C
_
1
3
8
1
3
9
L
G
N
D
_
1
3
9
1
4
0
R
D
2
-
1
4
1
R
D
2
+
1
4
2
R
E
2
-
1
4
3
R
E
2
+
1
4
4
L
G
N
D
_
1
4
4
1
4
5
Y
3
D
E
C
2
Y
1
V
S
Y
N
C
C
1
Y
7
C
L
K
Y
4
C
5
Y
6
C
3
Y
0
C
6
C
4
Y
5
Y
2
H
S
Y
N
C
C
0
C
6
0
3
0
.
1
u
2
5
V
C
6
0
4
0
.
1
u
2
5
V
C
6
0
5
0
.
1
u
2
5
V
C
6
0
6
0
.
1
u
2
5
V
C610
0.1u
25V
C612
0.1u
25V
C613
0.1u
25V
C
6
2
0
0
.
1
u
2
5
V
C
6
1
9
0
.
1
u
2
5
V
C
6
1
8
0
.
1
u
2
5
V
C
6
1
7
0
.
1
u
2
5
V
C
6
1
5
0
.
1
u
2
5
V
C614
0.1u
25V
C611
0.1u
25V
C609
0.1u
25V
C608
0.1u
25V
F
B
6
0
1
FB603
C
6
1
6
0
.
1
u
2
5
V
R
6
1
0
1
0
k
R
6
1
2
1
0
k
R
6
1
1
1
0
k
R
6
0
6
1
0
0
R
6
0
7
1
0
0
R
6
0
8
1
0
0
R
6
0
9
1
0
0
S
6
0
1
R613
10k
R
6
1
4
1
0
k
G
N
D
C
7
R
6
1
5
1
0
k
1
0
0
•
•
I
m
p
e
d
a
n
c
e
S
W
1
,
2
:
a
d
j
u
s
t
d
e
l
a
y
S
W
3
:
s
w
i
t
c
h
L
V
D
1
0
2
4
R
/
F
3
0
p
i
n
C
o
a
x
i
a
l
8
l
a
n
e
• No.1 and 2 of S601 adjust the signal delay. No.3 selects whether to input the rising edge or falling edge of the
signal.