Sony CDX-C8850R, Руководство по обслуживанию

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Pin No. Pin Name I/O Pin Description
74 SIN I Serial data input (Fixed at “L” in this set.)
75 BCK I Clock signal input for serial bit transfer of serial input/output data.
76 LRCK I Sampling frequency clock signal input of serial input/output data.
77 XMST I
Bit clock (BCK) and L/R sampling clock (LRCK) signal master/slave mode select
signal input from system control (IC500). (“L” : master mode, “H” : slave mode)
78 VDD3 — Digital power supply pin (+3.3 V)
79 AVSP — PLL system ground
80 PLLEN I PLL enable signal input (Normally, fixed at “L”.)
81 PLCLK O PLL clock signal output (Not used in this set.)
82 CKSTP I PLL clock output control signal input from system control (IC500).
83 AVDP — PLL system power supply pin (+3.3 V)
84 VSS4 — Digital ground
85 – 94 TD14 – 23 I Test pin (Normally, fixed at “L”.)
95 VDD4 — Digital power supply pin (+3.3 V)
96 AVSD — Ground (for D-RAM)
97 SCLI I Not used. (Normally, fixed at “L”.)
98 BIM I Not used. (Normally, fixed at “L”.)
99 SDRAM I Not used. (Normally, fixed at “L”.)
100 AVDD — Power supply pin (+3.3 V) (for D-RAM)