SONIX SN32F260 Series, Руководство пользователя

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SN32F260 Series
32-Bit Cortex-M0 Micro-Controller
SONiX TECHNOLOGY CO., LTD
Page 65
Version 1.5
6.7.4 CT16Bn Prescale Counter register (CT16Bn_PC) (n=0,1)
Address Offset: 0x0C
The 8-bit Prescale Counter controls division of PCLK by some constant value before it is applied to the Timer Counter.
This allows control of the relationship between the resolution of the timer and the maximum time before the timer
overflows. The Prescale Counter is incremented on every PCLK. When it reaches the value stored in the Prescale
Register, the Timer Counter is incremented, and the Prescale Counter is reset on the next PCLK. This causes the TC
to increment on every PCLK when PR = 0, every 2 PCLKs when PR = 1, etc.
Bit Name Description Attribute Reset
31:8 Reserved R 0
7:0
PC[7:0] Prescale Counter. R/W 0
6.7.5 CT16Bn Count Control register (CT16Bn_CNTCTRL) (n=0)
Address Offset: 0x10
This register is used to select between Timer and Counter mode, and in Counter mode to select the pin and edges for
counting.
When Counter Mode is chosen as a mode of operation, the CAP input (selected by the CIS bits) is sampled on every
rising edge of the PCLK clock. After comparing two consecutive samples of this CAP input, one of the following four
events is recognized: rising edge, falling edge, either of edges or no changes in the level of the selected CAP input.
Only if the identified event occurs, and the event corresponds to the one selected by CTM bits in this register, will the
Timer Counter register be incremented.
Effective processing of the externally supplied clock to the counter has some limitations. Since two successive rising
edges of the PCLK clock are used to identify only one edge on the CAP selected input, the frequency of the CAP input
cannot exceed one half of the PCLK clock. Consequently, the duration of the HIGH/LOW levels on the same CAP input
in this case cannot be shorter than 1/ (2 x PCLK).

Note: If Counter mode is selected, bit2~0 of Capture Control (CAPCTRL) register must be programmed as
0x0.
Bit Name Description Attribute Reset
31:4 Reserved R 0
3:2 CIS[1:0]
Count Input Select.
In counter mode (when CTM[1:0] are not 00), these bits select which
CAP0 pin is sampled for clocking.
00: CT16Bn_CAP0
Other: Reserved.
R/W 0
1:0 CTM[1:0]
Counter/Timer Mode.
This field selects which rising PCLK edges can
increment Timer’s
Prescale Counter (PC), or clear PC and increment Timer Counter (TC).
00: Timer Mode: every rising PCLK edge
01: Counter Mode: TC is incremented on rising edges on the CAP0 input
selected by CIS bits.
10: Counter Mode: TC is incremented on falling edges on the CAP0 input
selected by CIS bits.
11: Counter Mode: TC is incremented on both edges on the CAP0 input
selected by CIS bits.
R/W 0