SONiX TECHNOLOGY CO. SN8F22711B, Руководство пользователя

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SN8F2270B Series
USB 2.0 Low-Speed 8-Bit Micro-Controller
SONiX TECHNOLOGY CO., LTD
Page 106
Version 1.3
12
INSTRUCTION TABLE
Field Mnemon D ic escription C DC Z Cycle
MOV A,M
M
-
√
A
←
- 1
M MOV M,A
←
A
- -
M
- 1
O B0MOV A,M A
←
M (bank 0)
- -
√
1
V B0MOV M,A M (bank 0)
←
A
- - - 1
E A,I - MOV
A
←
I
- - 1
B0MOV M,I M
←
I, “M” only supports 0x80~0x87 registers (e.g. PFLAG,R,Y,Z…)
- - - 1
XCH A,M M - - - A
←→
1+N
B0XCH A,M
M (bank 0)
- - -
A
←→
1+N
MOVC
R, A
←
ROM [Y,Z]
- - - 2
ADC A,M
A
←
A + M + C, if occur carry, then C=1, else C=0
√ √ √
1
A ADC M,A M
←
A + M + C, if occur carry, then C=1, else C=0
√ √ √
1+N
R ADD A,M A ( A + M, if occur carry, then C=1, else C=0
√ √ √
1
I ADD M,A M ( A + M, if occur carry, then C=1, else C=0
√ √ √
1+N
T B0ADD M,A M (bank 0) ( M (bank 0) + A, if occur carry, then C=1, else C=0
√ √ √
1+N
H ADD A,I A ( A + I, if occur carry, then C=1, else C=0
√ √ √
1
M SBC A,M A ( A - M - /C, if occur borrow, then C=0, else C=1
√ √ √
1
E SBC M,A M ( A - M - /C, if occur borrow, then C=0, else C=1
√ √ √
1+N
T SUB A,M A ( A - M, if occur borrow, then C=0, else C=1
√ √ √
1
I SUB M,A M ( A - M, if occur borrow, then C=0, else C=1
√ √ √
1+N
C SUB A,I A
←
A - I, if occur borrow, then C=0, else C=1
√ √ √
1
AND A,M
A
←
A and M
- -
√
1
L AND M,A M
←
A and M
- -
√
1+N
O AND A,I A
←
A and I
- -
√
1
G OR A,M A
←
A or M
- -
√
1
I OR M,A
M
←
A or M
- -
√
1+N
C O - -
√
1 R A,I A
←
A or I
XOR A,M
A
←
A xor M
- -
√
1
XOR M,A
M
←
A xor M
- -
√
1+N
X - -
√
1 OR A,I A
←
A xor I
SWAP M A (b3~b0, b7~b4)
←
M(b7~b4, b3~b0)
- - - 1
P SWAPM M M(b3~b0, b7~b4)
←
M(b7~b4, b3~b0)
- - - 1+N
R RRC M A
←
RRC M
√
- - 1
O RRCM M M
←
RRC M
√
- - 1+N
C RLC M A
←
RLC M
√
- - 1
E RLCM M M
←
RLC M
√
- - 1+N
S CLR M M
←
0
- - - 1
S BCLR M.b M.b
←
0
- - - 1+N
BSET M.b
←
1
- - - 1+N
M.b
B0BC R
0)
←
0
- - - 1+N L M.b M(bank
.b
B0BS T
0)
←
1
- - 1+N E M.b M(bank
.b
-
CMP
A I, If A = I, th skip next instr n
-
√
1 + S RS A,I ZF,C
←
- en uctio
√
B CMPRS
←
A , If A = M, then skip next instruction
-
√
1 + S A,M ZF,C
– M
√
R INCS
M + If A = 0, then skip next instruction
- 1+ S M A
←
1,
- -
A INCMS M
←
M + 1, If M = 0, then skip next instruction
- - - 1+N+S
M
N M - 1, f A = 0, then skip next instruction - 1+ S DECS M A
←
I - -
C DECMS M M
←
M - 1, If M = 0, then skip next instruction
- - - 1+N+S
H b = 0, en skip next in - - - 1 + S BTS0 M.b If M. th struction
M.b = 1, en skip next in - - - 1 + S BTS1 If M.b th struction
M (bank 0).b = 0, then skip next instruction - - - 1 + S B0BTS0 .b If M
1 bank .b = 1, then skip next instruction - - - 1 + S B0BTS M.b If M( 0)
JMP d
PC15/14
←
RomPages1/0, PC13~PC0
←
d
- - - 2
CALL d
←
PC15~PC0, PC15/14
←
RomPages1/0, PC13~P d
- - - 2
Stack C0
←
M RET
PC
←
Stack
- - - 2
I Stac and to enable global interrupt - - 2 RETI PC
←
k, -
S sh ACC and PFLAG ( xcept NT0, NPD bit) int s. - - 1 PUSH To pu e o buffer -
C
POP To pop ACC and PFLAG ( ept NT0, NPD bit) from buffers.
√ √ √
1 exc
NOP No operation - - - 1
Note: 1. “M re ter or RAM ” is syste registers then “N” = 0, otherwise “N” = 1. ” is system gis . If “M m
2. If branch condition is true then “S = 1”, otherwise “S = 0”.