SOLTEK SL-75DRV, Руководство пользователя, Страница: 67 / 99

Chapter 4 BIOS Setup
67
* Current FSB Fre-
quency
This item allows you to control the FSB Frequency.
DRAM CLOCK/DRIVE CONTROL
Current FSB Frequency
DRAM Clock
DRAM Timing
SDRAM Cycle Length
Bank Interleave
DRAM Command Rate
Item Help
Menu Level
CMOS Setup Utility - Copyright (C) 1984-2001 Award Software
DRAM Clock/Drive Control
:Move Enter:/-/PU/PD:Value F10:Save ESC:Exit F1:General Help
F5:Previous Values F6:Fail-Safe Defaults F7:Optimized Defaults
100MHz
100MHz
By SPD
2.5
Disabled
1T Command
* DRAM Clock The value represents the performance parameters
of the installed memory chips (DRAM). Do not
change the value from the factory setting unless you
install new memory that has a different performance
rating.
* DRAM Timing When this item Enabled, DRAM Timing is set by
SPD.
SPD (Serial Presence Detect) is located on the
memory modules, BIOS reads information coded in
SPD during system boot up.
* SDRAM Cycle Length
Select CAS latency time in HCLKs of 2 or 3. The
system designer already set the values. Do not
change the default value unless you change speci-
fications of the installed DRAM or the installed CPU.
* Bank Interleave
The choices: Disabled; 2 Bank; 4 Bank.