65ME/65ME+
53
Video BIOS Cacheable
Choose Enabled or Disabled (default). When enabled,
the access to the VGA BIOS addressed is cached.
System BIOS
Cacheable
Choose Enabled or Disabled (default). When enabled,
the access to the system BIOS ROM addressed at
F0000H - FFFFFH is cached.
SDRAM CAS Latency
Time
When synchronous DRAM is installed, the number of
clock cycles of CAS latency depends on the DRAM
timing.
The choice:2,3
Memory Hole At 15M-
16M
In order to improve performance, certain space in
memory is reserved for ISA cards. This memory must
be mapped into the memory space below 16MB.
The choice: 15M-16M, Disabled.
SDRAM Cycle Time
Tras/Trc
Select the number of SCLKs for an access cycle.
The choice:5/7,7/9
SDRAM RAS-To-CAS
Delay
This field lets you insert a timing delay between the
CAS and RAS strobe signals, used when DRAM is
written to, read from, or refreshed. Fast gives faster
p e r f o r m a n c e a n d S l o w g i v e s m o r e s t a b l e
performance. This field applies only when synchro-
nous DRAM is installed in the system.
The Choice:2,3
SDRAM RAS
Precharge Time
If an insufficient number of cycles is allowed for the
RAS to accumulate its charge before DRAM refresh,
the refresh may be incomplete and the DRAM may
fail to retain data. Fast gives faster performance;and
Slow gives more stable performance. This field ap-
plies only when synchronous DRAM is installed in
the system.
The Choice:2,3
CPU Latency Timer
Use Default setting.