SOLTEK SL-65DV2, Руководство пользователя, Страница: 53 / 72

65DVB/65DV2
53
CPU to PCI Write
Buffer
When this field is Enabled, writes from the CPU to
the PCI bus are buffered, to compensate for the speed
differences between the CPU and the PCI bus. When
Disabled, the writes are not buffered and the CPU
must wait until the write is complete before starting
another write cycle.
The choice: Enabled, Disabled.
PCI Dynamic Bursting When Enabled, every write transaction goes to the
write buffer. Bursting transactions then burst on the
PCI bus and non-bursting transactions don’t.
The choice: Enabled, Disabled.
PCI Master 0 WS Write When Enabled, writes to the PCI bus are executed
with zero wait states.
The choice: Enabled, Disabled.
PCI Delay Transaction Leave this field at default
PCI #2 Access #1 Retry Leave this field at default
AGP Master 1 ws write Leave this field at default
AGP Master 1 ws read Leave this field at default
AGP Aperture Size Choose 4, 8, 16, 32, 64, 128 or 256 MB. Memory
mapped and graphics data structures can reside in a
Graphics Aperture. This area is like a linear buffer.
BIOS will automatically report the starting address of
this buffer to the O.S.
AGP-2X Mode This item allows you to enable / disable the AGP-2X
mode.
Video RAM Cacheable Choose Enabled or Disabled. When enabled, the
access to the VGA RAM addressed is cached.