High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface
Datasheet
Revision 1.4 (08-19-08)
438
SMSC LAN9312
DATASHEET
14.5.4.27
Buffer Manager Interrupt Pending Register (BM_IPR)
This register contains the Buffer Manager interrupt status. The status is double buffered. All interrupts
in this register may be masked via the
Buffer Manager Interrupt Mask Register (BM_IMR)
Chapter 5, "System Interrupts," on page 49
for more information.
Register #:
1C21h
Size:
32 bits
BITS
DESCRIPTION
TYPE
DEFAULT
31:14
RESERVED
RO
-
13:10
Drop Reason B
When bit 7 is set, these bits indicate the reason a packet was dropped per
the table below:
RC
0h
9:8
Source Port B
When bit 7 is set, these bits indicate the source port on which the packet
was dropped.
00 = Port 0
01 = Port 1
10 = Port 2
11 = RESERVED
RC
00b
7
Status B Pending
When set, bits 13:8 are valid.
RC
0b
BIT
VALUES
DESCRIPTION
0000
The destination address was not in the ALR table (unknown or broadcast), and
the Broadcast Buffer Level was exceeded.
0001
Drop on Red was set and the packet was colored Red.
0010
There were no buffers available.
0011
There were no memory descriptors available.
0100
The destination address was not in the ALR table (unknown or broadcast) and
there were no valid destination ports.
0101
The packet had a receive error and was >64 bytes
0110
The Buffer Drop Level was exceeded.
0111
RESERVED
1000
RESERVED
1001
Drop on Yellow was set, the packet was colored Yellow and was randomly
selected to be dropped.
1010
RESERVED
1011
RESERVED
1100
RESERVED
1101
RESERVED
1110
RESERVED
1111
RESERVED