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SiTime SiT15 Series Скачать руководство пользователя страница 28

The Smart Timing Choice™

28

SiT-AN10037 Rev 1.3

SiT15xx Optimized Drive Settings

Table 34: Main Clock Source Update Enable Register MAINCLKUEN

Bit

Symbol

Value

Description

Reset Value

0

ENA

Enable main clock source update

1

0

No change

1

Update clock source

31:1

-

-

Reserved

-

Table 35: CLKOUT Clock Source Update Enable Register CLKOUTUEN

Bit

Symbol

Value

Description

Reset Value

0

ENA

Enable CLKOUT clock source update

1

0

No change

1

Update clock source

31:1

-

-

Reserved

-

15

Appendix F: Programming the Freescale Kinetis L4x and
L5x System Oscillator

15.1

Programming Model

The MCU incorporates two modules managing a clock distribution. The selection and multiplexing of
system clock sources is controlled and programmed via the multipurpose clock generator (MCG) module.
The setting of clock dividers and module clock gating for the system are programmed via the system
integration module (SIM). The system oscillator, MCG and SIM registers control the multiplexers, dividers
and clock gates.

NOTE. After OSC is enabled and starts generating clocks, the configurations such as low power
and frequency range must not be changed.

The oscillator module has built-in load capacitors for a connected crystal. OSC0_CR controls low power
modes operation and the load capacitors. If ERCLKEN and EREFSTEN in OSC0_CR are set, the OSC is
in operation when the MCU enters Stop modes.

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Содержание SiT15 Series

Страница 1: ...Programming the STMicroelectronics STM32 LSE Oscillator 13 11 1 Low speed External Clock Oscillator 13 11 2 External Clock Source LSE bypass 14 11 3 Clock Security System on LSE 14 11 4 Clock out Capability 14 11 5 Configuring LSE 15 12 Appendix C Programming the Renesas Electronics RL78G13 XT1 Oscillator 16 12 1 XT1 Oscillator 16 12 2 Configuration XT1 16 13 Appendix D Programming the Texas Instr...

Страница 2: ...imized for each of the 32 kHz oscillator modes is provided for the following MCUs 1 Energy Micro EFM32 2 Renesas Electronics RL78G13 3 STMicroelectronics STM32 4 Texas Instruments MSP430F2x 5 NXP LPC11xx 6 Freescale Kinetis L4x L5x The programming details specific to each MCU are listed in individual Appendices at the end of this application note 2 MCU 32 kHz Oscillator Operating Modes Most energy...

Страница 3: ...lator Disabled 1 2 4 3 VDD GND Mode 2 Oscillator ON and driven by SiT153x NanoDrive output Mode 1 Oscillator ON and driven by external quartz resonator Mode 1 Oscillator ON and driven by SiT153x NanoDrive output C1 and C2 are optional and can be removed for additional power savings Mode 3 Oscillator OFF Bypassed and driven by external logic level square wave signal B C A 250 mV Mode 3 Oscillator O...

Страница 4: ...ls VOL VOH 1 225 1 100 1 000 0 900 0 800 0 700 0 600 0 800 D28 D18 D08 0 700 D27 D17 D07 D97 0 525 D26 D16 D06 D96 D86 0 500 D25 D15 D05 D95 D85 D75 0 400 D14 D04 D94 D84 D74 D64 0 350 D13 D03 D93 D83 D73 D63 The supported AC coupled settings shown in Table 2 should be used with 32 kHz oscillator modes which are insensitive to DC bias levels thus only the NanoDrive swing is relevant The part numbe...

Страница 5: ...Figure 4 shows the waveform of SiT15xxAI H4 DCC 32 768 1 8V VDD at room temperature in to a 15 pF load Figure 4 LVCMOS waveform of a SiT15xxAI H4 DCC 32 768 at 1 8V VDD in to 15 pf load LVCMOS level setting should be used if the NanoDrive settings do not achieve the expected results and best results and lowest power will be achieved when the on chip oscillator has been bypassed or disabled as illu...

Страница 6: ...le disable and program various operating modes of the EFM32 LFXO oscillator 5 STMicroelectronics STM32 The STM32L152RBT6 is an ARM based Cortex M3 MCU The internal RTC has a separate accurate low frequency LSE oscillator The LSE oscillator has the advantage of providing a low power but highly accurate clock source for the real time clock RTC peripheral clock calendar or other timing functions The ...

Страница 7: ...6 for MCU VDD 1 8V recommended for lowest power Appendix C provides details on how to enable disable and program various operating modes of the RL78G13 XT1 oscillator 7 Texas Instruments MSP430F2x MSP430 microcontrollers from Texas Instruments are based on a 16 bit RISC CPU The architecture combined with five different low power modes is optimized to achieve extended battery life in portable appli...

Страница 8: ...s L4x L5x The Kinetis L series MCUs are based on ARM Cortex M0 processors These processors feature low power consumption in conjunction with a high performance The clock distribution system of the MCU includes Multipurpose Clock Generator MCS Crystal Oscillator XOSC and Real Time Clock RTC modules A quartz crystal can be connected to the EXTAL0 and XTAL0 pins If the XOSC is bypassed an external cl...

Страница 9: ...4 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0 0x0 0x3 0 1 0x0 0x3 0 0x1 0x3 0x0 Access RW RW RW RW RW RW RW RW RW RW RW Name CLKOUTSEL1 CLKOUTSEL0 LFXOTMEOUT LFXOBUFCUR LFXOBOOST LFXOMODE HFXOTMEOUT HFXOGLITCHDETEN HFXOBUFCUR HFXOBOOST HFXOMODE Table 10 The LFXOMODE Field Value Mode Description 0 XTAL 32 768 kHz crystal oscillator 1 BUFEXTCLK An AC coupled buffer is coupl...

Страница 10: ...re devices always write bits to 0 9 LFXODIS Disables the LFXO LFXOEN has higher priority if written simultaneously 0 W1 LFXO Disable 8 LFXOEN Enables the LFXO 0 W1 LFXO Enable 7 LFRCODIS Disables the LFRCO LFRCOEN has higher priority if written simultaneously 0 W1 LFRCO Disable 6 LFRCOEN Enables the LFRCO 0 W1 LFRCO Enable 5 AUXHFRCODIS Disables the AUXHFRCO AUXHFRCOEN has higher priority if writt...

Страница 11: ...RDY HFRCOENS Table 14 CMU_STATUS The 14 8 Field Descriptions Bit Name Reset Access Description 31 15 Reserved To ensure compatibility with future devices always write bits to 0 14 CALBSY Calibration is on going 0 R Calibration Busy 13 LFXOSEL LFXO is selected as HFCLK clock source 0 R LFXO Selected 12 LFRCOSEL LFRCO is selected as HFCLK clock source 0 R LFRCO Selected 11 HFXOSEL HFXO is selected a...

Страница 12: ...___________________________ CMU CTRL 0x3 11 CMU CTRL 0x00000000 XTAL 32768 Hz crystal oscillator CMU CTRL 0x00000800 BUFEXTCLK AC coupled CMU CTRL 0x00001000 DIGEXTCLK an external clock source Lock CMU_CTRL CMU OSCENCMD 0x1UL 8 Wait for clock to stabilize if requested Applicable only for crystal oscillator configuration if wait while CMU STATUS 0x1 9 _______________________________________________...

Страница 13: ... Reserved RTCSEL 1 0 rw rw rw rw 15 14 13 12 11 10 9 8 Reserved LSECS SD LSECS SON LSE BYP LSERDY LSEON r rw rw r rw 7 6 5 4 3 2 1 0 Reserved LSI RDY LSION r rw The LSERDY flag in the RCC_CSR 9 register indicates whether the LSE crystal is stable or not At startup the LSE crystal output clock signal is not released until this bit is set by hardware An interrupt can be generated if enabled in the R...

Страница 14: ...elected by RTCSEL The CSS on LSE is working in all modes Run Sleep Stop and Standby If a failure is detected on the external 32 kHz oscillator the LSE clock is no longer supplied to the RTC but no hardware action is made to the registers In Standby mode a wakeup is generated In other modes an interrupt can be sent to wake up The software MUST then disable the LSECSSON bit stop the defective 32 kHz...

Страница 15: ...wever when the HSE clock is used as RTC clock source the RTC cannot be used in Stop and Standby low power modes 11 5 Configuring LSE 1 Reset LSEON 8 and LSEBYP 10 bits in RCC_CSR before configuring the LSE IAR Embedded Workbench IDE example define RCC_LSE_OFF uint8_t 0x00 Reset LSEON and LSEBYP bits before configuring the LSE __IO uint8_t CSR_BYTE2_ADDRESS RCC_LSE_OFF 2 Set the new LSE configurati...

Страница 16: ...n mode AMPHS1 AMPHS0 if required 3 Set the oscillator mode by setting clearing EXCLKS OSCSELS fields in the CMC register Table 20 4 Clear the XTSTOP bit in CSC 6 Table 19 to enable the XT1 oscillator Table 19 CSC Register Symbol 7 6 5 4 3 2 1 0 CSC MSTOP XTSTOP 0 0 0 0 0 HIOSTOP MSTOP High speed system clock operation control X1 oscillation mode External clock input mode Input port mode 0 X1 oscil...

Страница 17: ...ion 1 0 Input port mode Input port 1 1 External clock input mode Input port External clock input EXCLKS OSCSELS Subsystem clock pin operation mode XT1 P123 pin XT2 EXCLKS P124 pin 0 0 Input port 0 1 Crystal resonator connection 1 0 Input port 1 1 Input port External clock input AMPHS1 AMPHS0 XT1 oscillator oscillation mode selection 0 0 Low power consumption oscillation default 0 1 Normal oscillat...

Страница 18: ...select the range of operation LFXT1 may be used with an external clock signal on the XIN pin in either LF or HF mode when LFXT1Sx 11 OSCOFF 0 and XCAPx 00 When used with an external signal the external frequency must meet the data sheet parameters for the chosen mode When the input frequency is below the specified lower limit the LFXT1OF bit may be set preventing the CPU from being clocked with LF...

Страница 19: ...y range for LFXT1 when XTS 1 When XTS 0 When XTS 1 00 32768 Hz crystal on LFXT1 00 0 4 to 1 MHz crystal 01 Reserved 01 1 to 3 MHz crystal 10 VLOCLK 10 3 to 16 MHz crystal 11 External clock source 11 0 4 to 16 MHz clock source XCAPx Bits 3 2 Oscillator capacitor selection These bits select the effective capacitance seen by the LFXT1 crystal when XTS 0 If XTS 1 or if LFXT1Sx 11 XCAPx should be 00 00...

Страница 20: ...et 1 1 Secondary peripheral module function is selected 13 3 Low power Modes The MSP430 devices have several low power modes Every LPMx low power mode allows developers to create an application with balanced power consumption The low power modes are configured with the CPUOFF OSCOFF SCG0 and SCG1 bits in the status register The advantage of including the CPUOFF OSCOFF SCG0 and SCG1 mode control bi...

Страница 21: ...t enabled 31 1 Reserved There is no possibility to bypass the RTC oscillator The external clock should be applied to the RTCXIN pin 14 2 Clock Output Capability The LPC1100 devices feature a clock output function that routes the IRS oscillator the system oscillator the watchdog oscillator or the main clock to an output pin You can configure the MCU to get 32768 Hz clock from an I O pin for on boar...

Страница 22: ...e as the clock source for the PLL LPC_SYSCTL SYSPLLCLKSEL 0x3 7 updated clock source for PLL LPC_SYSCTL SYSPLLCLKUEN 0 LPC_SYSCTL SYSPLLCLKUEN 1 update clock source for the main clock domain LPC_SYSCTL MAINCLKUEN 0 LPC_SYSCTL MAINCLKUEN 1 update clock source for CLKOUT LPC_SYSCTL CLKOUTUEN 0 LPC_SYSCTL CLKOUTUEN 0x1 ...

Страница 23: ... 1 0 Disable 1 Enable 2 RAM0 Enables clock for Main SRAM0 1 0 Disable 1 Enable 3 FLASHREG Enables clock for flash register interface 1 0 Disable 1 Enable 4 FLASHARRAY Enables clock for flash access 1 0 Disable 1 Enable 5 I2C0 Enables clock for I2C 0 0 Disable 1 Enable 6 GPIO Enables clock for GPIO port registers 1 0 Disable 1 Enable 7 CT16B0 Enables clock for 16 bit counter timer 0 0 0 Disable 1 E...

Страница 24: ...r WWDT 0 0 Disable 1 Enable 16 IOCON Enables clock for I O configuration block 0 0 Disable 1 Enable 17 Reserved 0 18 SSP1 Enables clock for SSP1 0 0 Disable 1 Enable 19 PINT Enables clock to GPIO Pin interrupt register interface 0 0 Disable 1 Enable 20 USART1 Enables clock to USART1 register interface 0 0 Disable 1 Enable 21 USART2 Enables clock to USART2 register interface 0 0 Disable 1 Enable 22...

Страница 25: ...1 Enable 27 USBSRAM Enables USB SRAM SRAM2 block located at 0x2000 4000 to 0x2000 4800 1 0 Disable 1 Enable 28 CRC Enables clock for CRC 0 0 Disable 1 Enable 29 DMA Enables clock for DMA 0 0 Disable 1 Enable 30 RTC Enables clock for RTC register interface 0 0 Disable 1 Enable 31 SCT0_1 Enables clock for SCT0 and SCT1 0 0 Disable 1 Enable Table 28 Main Clock Source Select MAINCLKSEL Bit Symbol Valu...

Страница 26: ...input 0 0 Input not inverted HIGH on pin reads as 1 1 Input inverted HIGH on pin reads as 0 9 7 Reserved 0 10 OD Open drain mode 0 0 Disable 1 Enable Open drain mode enabled 12 11 S_MODE Digital filter sample mode 0 0x0 Bypass input filter 0x1 1 clock cycle 0x2 2 clock cycles 0x3 3 clock cycles 15 13 CLKDIV Select peripheral clock divider for input filter sampling clock IOCONCLKDIV Value 0x7 is re...

Страница 27: ... 1 Divide by 1 to 255 Divide by 255 31 8 Reserved 0 Table 32 System PLL Clock Source Select SYSPLLCLKSEL Bit Symbol Value Description Reset Value 1 0 SEL System PLL clock source 0 0x0 IRC 0x1 System oscillator Crystal Oscillator 0x2 Reserved 0x3 32 kHz clock Select this option when the 32 kHz clock is the clock source for the main clock and select the pll input in the MAINCLKSEL register Do not us...

Страница 28: ...incorporates two modules managing a clock distribution The selection and multiplexing of system clock sources is controlled and programmed via the multipurpose clock generator MCG module The setting of clock dividers and module clock gating for the system are programmed via the system integration module SIM The system oscillator MCG and SIM registers control the multiplexers dividers and clock gat...

Страница 29: ...e clock is inactive 1 External reference clock is enabled 6 Reserved This read only field is reserved and always has the value 0 5 EREFSTEN External Reference Stop Enable Controls whether or not the external reference clock OSCERCLK remains enabled when MCU enters Stop mode 0 External reference clock is disabled in Stop mode 1 External reference clock stays enabled in Stop mode if ERCLKEN is set b...

Страница 30: ...cted for the crystal oscillator 1x Encoding 2 Very high frequency range selected for the crystal oscillator 3 HGO0 High Gain Oscillator Select Controls the crystal oscillator mode of operation See the Oscillator OSC chapter for more details 0 Configure crystal oscillator for low power operation 1 Configure crystal oscillator for high gain operation 2 EREFS0 External Reference Select Selects the so...

Страница 31: ...the CLKS bits due to internal synchronization between clock domains 00 Encoding 0 Output of the FLL is selected reset default 01 Encoding 1 Internal reference clock is selected 10 Encoding 2 External reference clock is selected 11 Reserved 1 OSCINIT0 OSC Initialization This bit which resets to 0 is set to 1 after the initialization cycles of the crystal oscillator clock have completed After being ...

Страница 32: ...or the TPM counter clock 00 Clock disabled 01 MCGFLLCLK clock 10 OSCERCLK clock 11 MCGIRCLK clock 23 8 Reserved This field is reserved This read only field is reserved and always has the value 0 7 5 CLKOUTSEL CLKOUT select Selects the clock to output on the CLKOUT pin 000 Reserved 001 Reserved 010 Bus clock 011 LPO clock 1 kHz 100 MCGIRCLK 101 Reserved 110 OSCERCLK 111 Reserved 4 RTCCLKOUTSEL RTC ...

Страница 33: ...d indicates the current frequency range for DCOOUT The DRST field does not update immediately after a write to the DRS field due to internal synchronization between clock domains See the DCO Frequency Range table for more details 00 Encoding 0 Low range reset default 01 Encoding 1 Mid range 10 Encoding 2 Mid high range 11 Encoding 3 High range 4 1 FCTRIM Fast Internal Reference Clock Trim Setting ...

Страница 34: ...de and select external reference MCG_C2 0x3C 3 Select external reference MCG_C2 0x04 4 Wait for oscillator initialization has completed while MCG_S 0x2 0x2 15 2 Clock Output Capability The MCU has the RTC_CLKOUT pin that can be driven either with RTC 1 Hz or with the OSCERCLK on chip clock source Control for this option is through SIM_SOPT2 4 bit SIM_SOPT2 7 5 bits control the clock source Below i...

Страница 35: ...rehousing or transportation or v being subjected to unusual physical thermal or electrical stress Disclaimer SiTime makes no warranty of any kind express or implied with regard to this material and specifically disclaims any and all express or implied warranties either in fact or by operation of law statutory or otherwise including the implied warranties of merchantability and fitness for use or a...

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