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SH79F3283

7.9.4 Interrupt Flag

Each Interrupt source has its own interrupt flag, when interrupt occurs, corresponding flag will be set by hardware, the interrupt
flag bits are listed in interrupt abstract table.
When an external interrupt

INT0/1/2/3

is generated, if the interrupt was edge trigged, the flag IEx (x = 0-3) that generated this

interrupt is cleared by hardware when the service routine is vectored. If the interrupt was level trigged, then the requesting
external source directly controls the request flag, rather than the on-chip hardware.
When

INT4

generates an interrupt, the flag (IF4x (x = 0-7) in EXF1 register) that generated this interrupt should be cleared by

user’s program because the same vector entrance was used in INT4. But if INT4 is set up as level trigged, the flag can’t be
cleared by user’s program, it only be controlled by peripheral signal level that connect to INT source pin.
The

Timer2

interrupt is generated by the logical OR of flag TF2 in T2CON register, which is set by hardware. None of these

flags can be cleared by hardware after CPU responses to the interrupt, the flag must be cleared by software
When the

Timer3

counter overflow, set interrupt flag bit TF3 in T3CON to 1 to generate Timer3 interrupt. The flag will be

cleared automatically by hardware after CPU responses to the interrupt.
When the

Timer4

counter overflow, set interrupt flag bit TF4 in T4CON to 1 to generate Timer4 interrupt. The flag will be

cleared automatically by hardware after CPU responses to the interrupt.
When the

Timer5

counter overflow, set interrupt flag bit TF5 in T5CON to 1 to generate Timer5 interrupt. The flag will be

cleared automatically by hardware after CPU responses to the interrupt.
The

EUARTx(x = 0, 1)

interrupt

s is generated by the logical OR of flag RI and TI in SCON/SCON1 register, which is set by

hardware. Neither of these flags can be cleared by hardware when the service routine is vectored. In fact, the service routine
will normally have to determine whether it was the receive interrupt flag or the transmission interrupt flag that generated the
interrupt, so the flag must be cleared by software.
The

ADC interrupt

is generated by ADCIF bit in ADCON. If an interrupt is generated, the converted result in ADCDH/ADCDL

will be valid. If continuous compare function in ADC module is Enable, ADCIF will not be clear at each conversion when
conversion results is less than the compare value. But if converted result is larger than compare value, ADCIF bit will be 1.
The flag must be cleared by software.
The

SPI interrupt

are generated by SPIF in SPSTA or set MODF. The flags can be cleared by software.

The

SCM interrupt

is generated by SCMIF in CLKCON register, which is set by hardware. And the flag can only be cleared by

hardware.
The

LPD interrupt

is generated by LPDF in LPDCON register. And the flag can only be cleared by hardware. By setting the

LPDMD, can choose when the V

voltage is above or below the LPD set generated when the detecting voltage interruption of

LPD.
The

PWM interrupts