ICD-4000-OEM
© SightLine Applications, Inc.
15
Since SightLine supported cameras range from 10 MHz to 150 MHz in input pixel clock frequency, there
are several versions of FPGA code to support the varying PLL center frequencies. This PLL center
frequency is not dynamically adjustable.
The first FPGA version was generated at 148.5 MHz frequency (1080P60). It will work below 74.25
MHz( 1080P30/720P60). After more lower frequency FPGA versions were generated, the center
frequency was added to the name of the FPGA load.
Table 16
shows the most common FPGA versions.
IMPORTANT:
Use the version with a center frequency closest to the camera pixel clock rate.
Table 16: FPGA Version Names and Pixel Clock Support
FPGA Name Center Frequency (MHz) Min Frequency (MHz)
Max Frequency (MHz)
GEN_HD
148.5
74.25
150.00 (FPGA Max)
GEN_HD75
74.25
40
Not Tested
GEN_HD40
40
20
80
GEN_HD20
20
10
40
8.9
Horizontal Blanking Requirements
The MIPI data acquired by the 4000-OEM has the following characteristics:
•
Each line of video is a separate MIPI packet.
•
A packet header is at the start of each packet.
•
End-of-frame and start-of-frame packets indicate a full frame of video.
Most video formats provide blanking regions (non-active pixel areas) to help with acquisition.
Typically, there are several blanking lines of video at the start of a frame and multiple blanking pixels at
the start of each line of video.
The MIPI packet headers are sent during the blanking regions of video. This works for standard HD
formats (e.g., 1080P60, 720P60) as there are enough vertical blanking lines and horizontal blanking
pixels.
Some custom cameras (mostly IR Cameras) have greatly reduced blanking intervals to increase the
frame rates for a specified pixel clock.
In some cases, these blanking intervals are too small to provide enough time to send the additional
MIPI overhead.
To use the GEN_HDxx FPGA versions in
Table 16
the following criteria is required:
•
Two lines of vertical blanking at the start of a video frame.
•
64 pixels or more of total blanking in a single video line. This includes all horizontal timing where
pixel values are not active (not visible).
For cameras with less than 64 total horizontal blanking pixels, SightLine has developed versions of the
FPGA code that support between 1 and 64 total horizontal blanking pixels.
