SightLine EAN-4000-OEM, Руководство пользователя

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EAN-4000-OEM-MIPI-Cameras
© SightLine Applications, Inc. 15
Table B2: MIPI Acquisition Settings
MIPI Settings Setting Notes
mipi_txl=1
•
The number of Tx lanes.
•
Valid values are 1, 2, and 4.
•
Requires a parameter save and board reset.
•
Changing the number of Tx Lanes will update the TSettle count automatically.
mipi_clk=74
•
MIPI clock rate in MHz. This will vary based on camera input pixel clock.
•
This affects both the MIPI CSI frequency and the TSettle count.
•
The CSI frequency is comparable to a sampling rate, and the TSettle count the number of
samples where it looks for the packet. The CSI frequency changes in discrete intervals.
•
The CSI frequency will be either 100 MHz, 200 MHz, 266 MHz.
•
Used when the 4000-MIPI cannot acquire packets from a camera source due to packet
timing incompatibility with default driver settings.
•
Requires a parameter save and board reset.
The above parameter values shown in Table B2 and their effects can be seen in the debug port (Serial
0) output of the 4000-OEM. Accessing the debug serial port requires the use of the 4000-DEBUG board.
See the
ICD-4000-OEM for details.

The debug serial port output defaults to 115,200 baud.
The CSI Frequency is shown in the debug output line:
Setting csi frequency =100000000 pixel_clock =74000000
The pixel_clock value will be the clock value set in mipi_clk .
The TSettle Count and number of Tx Lanes are shown in the debug output line:
pixel_clock=74000000 settle_cnt = 4 lane=0x83
1 Lane = 0x81, 2 Lane = 0x83, 4 Lane = 0x8F
Table B3: Common values for MIPI CSI Frequency and TSettle
Pixel Clock Tx Lanes CSI Frequency TSettle Count
148.5 2 200 12
74.25 2 100 4
27 2 100 8
20 2 100 10
B4 FPGA I2C Control of Camera Acquisition (Optional)
The section describes how to control camera acquisition through I2C registers for custom designed
FPGAs. Although not required, implementing an I2C register interface may make it a more flexible
design.
The 4000-OEM FPGA supports programmable camera timing parameters. This allows using the same
FPGA code to support multiple camera types and resolutions. The camera timing parameters are
updated from the 4000-OEM acquisition settings into the FPGA I2C registers. This data is automatically
updated through the MIPI I2C bus to the FPGA.