EAN-4000-OEM-MIPI-Cameras
© SightLine Applications, Inc.
14
B2 MIPI Packet Timing
The following parameters will depend on the pixel clock rate of the camera:
IMPORTANT:
The high speed (HS) clock mode may require a new release of 4000-OEM firmware.
•
Low power states are used between short and long packets. See the CSI-2 packets in the previous
section. This means that timing during the transition from low power to high speed mode needs to
be specified. This is dependent on the pixel clock of the camera and therefore the MIPI Tx clock.
•
This timing is covered by T-HS-PREPARE and T-HS-ZERO:
▪
The timing diagram can be referenced in page 3 in the Tektronix
on Mipi timing.
▪
The timing parameters should be specified by the documentation in the MIPI IP package used
to generate the MIPI packets. This will be dependent on the camera pixel clock.
▪
Figure 11
shows how a scope trace can be used to measure and compare values as the FPGA
code is being developed. The trace in this example was taken off the N phase of Tx Lane 0 (the P
phase looks different).
Figure B1: MIPI Packet Low Power to High Speed Transition
B3 Acquisition Settings for MIPI Configuration - Tx Lanes and MIPI Clock Rate
The 4000-OEM needs MIPI transmit information to be able to detect and capture the MIPI packets.
The following new settings shown in
Table B2
are available in the 3.2.x software release. Settings are
set as comma separated values (CSV) in the
Options
field in the
Acquisition Settings
dialog.
Figure B2: Options Field - Mipi Acquisition Settings
