553BTechnical specifications
A.4 CPU 1214C
S7-1200 Programmable controller
682
System Manual, 11/2011, A5E02486680-05
Table A- 42 Performance
Type of instruction
Execution speed
Boolean
0.1 μs/instruction
Move Word
12 μs/instruction
Real math
18 μs/instruction
Table A- 43 Blocks, timers and counters supported by S7-1200
Element
Description
Type
OB, FB, FC, DB
Size
25 Kbytes (CPU 1211C and CPU 1212C)
50 Kbytes (CPU 1214C)
Quantity
Up to 1024 blocks total (OBs + FBs + FCs + DBs)
Address range for FBs, FCs,
and DBs
1 to 65535 (such as FB 1 to FB 65535)
Nesting depth
16 from the program cycle or start up OB; 4 from the time delay
interrupt, time-of-day interrupt, cyclic interrupt, hardware interrupt,
time error interrupt, or diagnostic error interrupt OB
Blocks
Monitoring
Status of 2 code blocks can be monitored simultaneously
Program cycle
Multiple: OB 1, OB 200 to OB 65535
Startup
Multiple: OB 100, OB 200 to OB 65535
Time-delay interrupts and
cyclic interrupts
4
1
(1 per event): OB 200 to OB 65535
Hardware interrupts (edges
and HSC)
50 (1 per event): OB 200 to OB 65535
Time error interrupts
1: OB 80
OBs
Diagnostic error interrupts
1: OB 82
Type
IEC
Quantity
Limited only by memory size
Timers
Storage
Structure in DB, 16 bytes per timer
Type
IEC
Quantity
Limited only by memory size
Counters
Storage
Structure in DB, size dependent upon count type
SInt, USInt: 3 bytes
Int, UInt: 6 bytes
DInt, UDInt: 12 bytes
1
Time-delay and cyclic interrupts use the same resources in the CPU. You can have only a total of 4 of these interrupts
(time-delay plus cyclic interrupts). You cannot have 4 time-delay interrupts and 4 cyclic interrupts.