Siemens ERTEC 200P, Руководство пользователя

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Copyright © Siemens AG 2016. All rights reserved 305 ERTEC 200P-2 Manual
Technical data subject to change Version 1.0
2.3.10.5 UART1…4
ERTEC 200P contains 4 UARTs (UART1…4).
UART1…4 is implemented with the ARM soft macro (PL011). This is
similar to the stand-
ard UART 16C550. A detailed description of the registers and individual functions can be
found in 'DDI0183F_uart_pl011_r1p4_trm.pdf' /15/ ( see chapter 7.2.)
The PL011 soft macro differs from the standard UART 16C550 as follows:
Receive FIFO trigger level can be set: 1/8, 1/4, 1/2, 3/4 or 7/8
The deltas from the modem status signals are not available
Internal register address mapping and the register bit functions differ
The following 16C550 features are not supported by PL011:
1.5 stop bits (only 1 or 2 stop bits are supported)
Independent 'Receive Clock'
The UARTs can be controlled by the GDMA (see 2.3.4.2.2) and by ARM926.
As the DMA request signals available at UART1…4 are not suitable for GDMA operation,
internal status signals are used from the FIFO controller and sent to the GDMA as DMA
request signals. The signals for controlling the transmitter and receiver separately over
one GDMA channel each (see 0)are as follows:
UART_RX-FIFO not empty:
The RX FIFO contains at least one character and is not empty. As the UART can-
not know when the last character was read in, the GDMA must operate in SINGLE-
byte access mode (AHB). 1 to 65536 characters can therefore be transferred per
DMA request; the job consists of a transfer entry.
UART_TX-FIFO half-full or less:
The TX FIFO is at least half empty and therefore has space for 8 characters. The
GDMA must operate in INCR8-byte access mode (AHB) to ensure that there is no
FIFO overrun. If the transfer length is not modulo 8, the remaining characters are
transferred by the GDMA controller with the INCR burst byte (undefined length). 1
to 65536 characters can therefore be transferred per DMA request; the job con-
sists of a transfer entry.
The following UART interrupts are connected to the ARM interrupt controller (IRQ5-12)
(2.3.2.14):
UART1-4_UARTINTR: Group interrupt (modem status, receive FIFO, transmit
FIFO, receive timeout, error);
individual interrupts can be masked
UART1-4_UARTEINTR: Error interrupt
UART supports the following external signals:
Transmit Data (TXD, Output)
Receive Data (RXD, Input)
Clear To Send (CTS, Input)
Data Carrier Detect (DCD, Input)
Data Set Ready (DSR, Input)