•
C/Qn: IO-Link data or configurable GPIO (not insulated)
•
DIn: dedicated digital input (not isolated)
•
4 x IO-Link master
•
IO-Link stack is implemented in FPGA (SoftCore)
•
Max. 0.7 A total output for 24 V supply voltage connections
•
Switching output:
°
Max. output 100 mA
°
Min. high output logic level: VCC – 3 V
°
Max. low output logic level: 3 V
°
Push/pull, NPN, PNP configurable
°
Max. IO-Link output frequency: 230 kHz
°
Max. IO output frequency: 30 kHz
•
Switching input:
°
Min. high input logic level: 12 V
°
Max. low input logic level: 4 V
°
Max. IO-Link input frequency: 230 kHz
°
Max. IO input frequency: 30 kHz
•
The digital inputs and outputs are not reverse polarity protected. The voltage at the
X1 inputs and outputs must never be higher than the 24 V supply voltage of the
SIM2000ST to prevent feedback.
6.4.3
X2 – POWER
Pin
Signal
Function
1
Shield
Shield
2
GND
Ground
3
24V IN1
Supply voltage 1
4
Shield
Shield
5
GND
Ground
6
24V IN2
Supply voltage 2
Additional notes:
•
24V IN1 and 24V IN2 are designed with redundancy
6.4.4
X3 – OUTPUT
Table 2: X3 - OUTPUT
Pin
Signal
Function
1
OUT1
Insulated digital switching output
2
OUT2
Insulated digital switching output
3
OUT3
Insulated digital switching output
4
OUT4
Insulated digital switching output
5
24 V IN (X3)
Supply voltage for switching outputs
6
GND ISO (X3)
Insulated reference potential for switching outputs and 24 V
IN (X3)
7
GND ISO (X3)
Insulated reference potential for switching outputs and 24 V
IN (X3)
8
GND ISO (X3)
Insulated reference potential for switching outputs and 24 V
IN (X3)
9
GND ISO (X3)
Insulated reference potential for switching outputs and 24 V
IN (X3)
10
GND ISO (X3)
Insulated reference potential for switching outputs and 24 V
IN (X3)
6
ELECTRICAL INSTALLATION
22
O P E R A T I N G I N S T R U C T I O N S | SIM2000ST
8020764/1FTA/2022-05-02 | SICK
Subject to change without notice
