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PCI Delay Transaction
The chipset has an embedded 32-bit posted write buffer to support
delay transactions cycles. Select Enabled to support compliance with
PCI specification version 2.1.
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The Choice: Enabled or Disabled.
Memory Hole
In order to improve performance, some space in memory can be
reserved for ISA cards.
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The Choice: Disabled or 15M-16M.
System BIOS Cacheable
Selecting Enabled allows caching of the system BIOS ROM at F0000h-
FFFFFh, resulting in better system performance. However, if any pro-
gram is written to this memory area, a system error may result.
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The choice: Enabled or Disabled.
Video RAM Cacheable
Selecting Enabled allows caching of the video RAM , resulting in better
system performance. However, if any program is written to this memory
area, a system error may result.
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The Choice: Enabled or Disabled.