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26 | Spark-100 HW user manual v1.3   

 

An 8GByte option is available as an ordering option. 

2.6.4

 

SD/eMMC interface 

The SPARK-100 has a single SD/MMC bus connected to the HPS. The HPS is connected via an internal 
multiplexer (TXS02612 - SDIO Port Expander by TI) to either an internal 4/8 bits wide eMMC or to an 
external 4 bits SD interface. 

The control of the mux is done by GPIO44 of the HPS, ‘0’ – eMMC, ‘1’ - external SD. The mux can be 
controlled also via an external pin P123 in the SMARC interface. 

The pin can be tight to the required mode or alternatively in order to leave the control to the software 
connect to an external pull up or pull down according to the required mode. 

2.6.5

 

Boot options 

The Altera SOC offers several boot options. These options are selected according to three pins (bsel 2-0). 
The Spark support only part of these options due to that bsel 0 is tight to '1' internally . The other two 
pins are connected to the SMARC interface, Bsel1 1 is P124 Bsel2 – P125 offering the following options: 

Bsel value  
 

Boot source 

Support 

000  

Reserved 

Not supported 

001   

FPGA (HPS-to-FPGA bridge) 

Supported both pins should be 
set '0' 

010   
 

1.8 V NAND flash memory 

Not supported 

011   
 

3.0 V NAND flash memory 

Not supported 

100 

1.8 V SD/MMC flash memory with external 
transceiver 

Not supported 

101 

3.0 V SD/MMC flash memory with internal 
transceiver*  

Supported, Bsel 1 should be tight 
to '0' 

110 

1.8 V SPI or quad SPI flash memory 
 

Not supported 

111 

 3.0 V SPI or quad SPI flash memory 

Supported, both pins should be 
left open 

 
* Note: If SD/eMMC mode is selected then the selection between SD and eMMC can be done as 
described in section 2.6.4. 

2.6.6

 

DDR memory 

The SPARK-100 integrates 32 bit wide DDR3 running at 400 MHz.  The basic configuration is two chips of 
256MBx16 (1GB solution). There is also an ordering options for 128MBx16 (512MB solution) and 
512MBx16(2GB solution). 

The DDR solution supports an 8 bit ECC option – special ordering option, contact 

[email protected]

  

for more details. 

Содержание Spark-100

Страница 1: ...Spark 100 Altera Cyclone V SOC System on Module Integration guide Revision 1 3...

Страница 2: ...2 2 Reset sources 10 2 3 HPS Interfaces 12 2 3 1 USB 12 2 3 2 Ethernet port 13 2 3 3 UART 13 2 3 4 CAN 13 2 3 5 I2C overview 14 2 3 6 I2C Mapping 15 2 3 7 SPI 17 2 3 8 JTAG 17 2 4 Clocks scheme 19 2...

Страница 3: ...ns 29 2 10 1 SMARC connector 30 Appendix 1 Hardware devices used on the SOM 32 Appendix 2 Qsys parameters for the Spark 33 Document Revision History Revision Date Description 1 0 12 6 2014 Initial ver...

Страница 4: ...r more details if needed review the Cyclone V user manual 1 1 SoM introduction The Spark 100 is an industrial embedded System On Module SoM based on Altera new Cyclone V SoC The Spark 100 offers a uni...

Страница 5: ...iagram The following diagram provides an overview of the SOM The following paragraphs will provide detailed description of the various parts of the SOM and how to use them in order to build a product...

Страница 6: ...5V 5 2 1 1 VCCBAT FPGA Encryption Key power The Altera SOC has an option to maintain an encryption key for FPGA configuration even if the system power is down For that pin S147 of the SMARC interface...

Страница 7: ...3V The selection is done by hardware and cannot be changed during operation Bank 4A 68 1 5V 1 8V 2 5V 3 3V The selection is done by hardware and cannot be changed during operation Bank 5A 16 1 8V Fix...

Страница 8: ...located on the SOM can be used for debug and prototype or via pins on the SMARC interface this option must be used in production Note the pins cannot be based on I Os set by software the pin state sho...

Страница 9: ...es The power levels of ports 3B and 4A can be set by dip switches located on the SPARK 100 board SW2 There is a single switch that sets the VCCPD power for both banks and two switches that set the pow...

Страница 10: ...tate sufficient for software to boot o Triggered by a power on reset and other sources e g push buttons on carrier board o Resets all HPS logic that can be reset o Affects all reset domains o This Res...

Страница 11: ...or The FPGA can also be reset by the SOC ARM core or by an IO pin on the FPGA fabric When using the 128 MB QSPI Flash memory as a boot source the warm reset does not work automatically due to configur...

Страница 12: ...cluding control endpoint Up to 16 host channels Supports generic root hub Automatic ping capability Configurable to OTG 1 3 and OTG 2 0 The card has two possible configurations for the USB usage based...

Страница 13: ...wo LED signals from the GE PHY are also connected to the SMARC edge connector MDC MDIO The Ethernet MDC MDIO signals are connected to the internal phy and are not available on the SMARC connector 2 3...

Страница 14: ...expanded to four I2C interfaces in order to meet the SMARC requirements providing I2C_Cam I2C_GP I2C_PM and I2C_LCD buses o The buses can be used for any other application according need o There are...

Страница 15: ...AM_D I2C_CAM _C Enables access to I2C devices on Carrier I2C_CAM in SMARC standard 1 I2C_GP_D I2C_GP _C Enables access to I2C devices on Carrier I2C_GP in SMARC standard 2 I2C_PM_D I2C_PM _C Enables a...

Страница 16: ...0 2 REF_CLK_SEL Out Select the clock generator source clock 0 Primary internal 1 Secondary external 0 3 CLK_SYNC Out Synchronize the clock generator 0 4 CLK_PDN Out Disable the clock generator clock...

Страница 17: ...n board 10 pins JTAG connector The JTAG signals are also connected to the SMARC connector an analog switch selects between the JTAG connector and the SMARC connector The selection is done by a switch...

Страница 18: ...The switches options are as follows JSEL0 0 FPGA in Chain default 1 FPGA not in chain JSEL1 0 JTAG connector default 1 SMARC connector Note For production the SOM provided without the JTAG connector...

Страница 19: ...Low Noise Synthesizer 265 fs rms Typical 1 ppm Frequency Error and Eliminates Jitter or Low Noise Jitter Cleaner 1 6 pSec need for Crystal Oscillators and Other rms Typical Jitter Any frequency using...

Страница 20: ...ck generator source 0 Primary internal 1 Secondary 0 3 CLK_SYNC connected to Pin 42 of the clock distributor Out Synchronize the clock generator clocks For the clock device 0 4 CLK_PDN connected to Pi...

Страница 21: ...ly Y4_N Pin 25 Altera device CLK0N Pin W11 FPGA clock input Y5_P Pin 29 Altera device CLK1P Pin V12 FPGA clock input If a single ended clock is needed use the P pin only Y5_N Pin 28 Altera device CLK1...

Страница 22: ...0 85 KLE A6 A5 pin out which means that all the pins of the FPGA in that configuration are supported and available on the SMARC interface However when the A2 or A4 25KLEs or 40KLEs devices are used th...

Страница 23: ...ply with a wide range of protocols and data rate standards On the Spark the transceivers are routed as differential pairs to support high speed applications The Spark also provide optional low jitter...

Страница 24: ...des are supported 00000 Fast Parallel 16 bits 00001 Fast Parallel16 bits Security enabled 00010 Fast Parallel16 bits Compressed enabled 00011 Fast Parallel Security enabled Compressed enabled 2 6 HPS...

Страница 25: ...00 is supports an internal I2C memory device Atmel AT24C01Ce located on I2C1 bus of the HPS offering 1Kbit I2C memory Can be used as secure boot Can be used as MAC address for the GE interface Note pa...

Страница 26: ...The other two pins are connected to the SMARC interface Bsel1 1 is P124 Bsel2 P125 offering the following options Bsel value Boot source Support 000 Reserved Not supported 001 FPGA HPS to FPGA bridge...

Страница 27: ...d in 1 No card SD_WP GPIO0 out SD card write protect Active Low GE Interrupt GPIO35 in Giga Ethernet Interrupt from PHY Active Low TEMP_ALM GPI3 in Temperature Sensor Alarm Active Low IO_INT GPI2 in I...

Страница 28: ...ser manual v1 3 Fixed interfaces like GE and USB RFU unused pins reserved for future use The full pin out of the Spark is available in a dedicated document SPARK pin out definition available on the Sh...

Страница 29: ...rding to the SMARC standard the full details are available at http www sget org standards smarc html The following figures are taken from the standard to show the physical dimensions of the module and...

Страница 30: ...rs from other vendors are available in the SMARC HW specification Vendor Vendor P N Stack Height Body Height Contact Plating Foxconn AS0B821 S43B H 1 5mm 4 3mm Flash Black Foxconn AS0B821 S43N H 1 5mm...

Страница 31: ...nn AS0B826 S55B H 2 7mm 5 5mm 10 u in Black Foxconn AS0B826 S55N H 2 7mm 5 5mm 10 u in Ivory Foxconn AS0B821 S78B H 5 0mm 7 8mm Flash Black Foxconn AS0B821 S78N H 5 0mm 7 8mm Flash Ivory Foxconn AS0B8...

Страница 32: ...12 TI SDIO port expander with voltage level translation AT24C01C Atmel I2C Compatible 2 wire Serial EEPROM 1 Kbit 128 x 8 USB3300 Microchip High speed USB host device or OTG phy USB3740 Microchip High...

Страница 33: ...33 Spark 100 HW user manual v1 3 Appendix 2 Qsys parameters for the Spark The following paragraph provides the HPS configuration used in the demo version provided for the Spark...

Страница 34: ...ed Care must be taken for interfaces which are connected to hardware devices located on the module like USB GE I2C etc For interfaces which are connected directly connected to Spark interface the conf...

Страница 35: ...35 Spark 100 HW user manual v1 3 Clock configuration...

Страница 36: ...36 Spark 100 HW user manual v1 3 DDR setting...

Страница 37: ...37 Spark 100 HW user manual v1 3...

Страница 38: ...38 Spark 100 HW user manual v1 3...

Страница 39: ...39 Spark 100 HW user manual v1 3...

Страница 40: ...40 Spark 100 HW user manual v1 3...

Страница 41: ...41 Spark 100 HW user manual v1 3...

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